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author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2016-10-19 14:24:32 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-10-21 16:44:06 -0400 |
commit | f00a98154ecaddf849b283dd5b7cbda0f6c8f90f (patch) | |
tree | d355cd9a5d87e6ca4282918ec267d010b77ccc8c | |
parent | 2fd1ee0ca784e4235766601d6a7ef52ba1f0c519 (diff) |
gpu: nvgpu: gv11b: enable correct interrupts
Enable stall and non-stall interupts for gv11b.
Support for replayable interrupts will be added later.
Hub interrupts are not enabled and they will be enabled
after non-replayabale fault handling is in place.
JIRA GV11B-11
Change-Id: I99cc470dae9d02f92e9fb3cb49186dabfed78875
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1239337
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index bc0aee2e..0111d6b3 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c | |||
@@ -20,7 +20,32 @@ | |||
20 | #include "gv11b/mc_gv11b.h" | 20 | #include "gv11b/mc_gv11b.h" |
21 | #include "hw_mc_gv11b.h" | 21 | #include "hw_mc_gv11b.h" |
22 | 22 | ||
23 | static void mc_gv11b_intr_enable(struct gk20a *g) | ||
24 | { | ||
25 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
26 | |||
27 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | ||
28 | 0xffffffff); | ||
29 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = | ||
30 | mc_intr_pfifo_pending_f() | ||
31 | | eng_intr_mask; | ||
32 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | ||
33 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
34 | |||
35 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | ||
36 | 0xffffffff); | ||
37 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = | ||
38 | mc_intr_pfifo_pending_f() | ||
39 | | mc_intr_priv_ring_pending_f() | ||
40 | | mc_intr_ltc_pending_f() | ||
41 | | mc_intr_pbus_pending_f() | ||
42 | | eng_intr_mask; | ||
43 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | ||
44 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | ||
45 | } | ||
46 | |||
23 | void gv11b_init_mc(struct gpu_ops *gops) | 47 | void gv11b_init_mc(struct gpu_ops *gops) |
24 | { | 48 | { |
25 | gp10b_init_mc(gops); | 49 | gp10b_init_mc(gops); |
50 | gops->mc.intr_enable = mc_gv11b_intr_enable; | ||
26 | } | 51 | } |