gpu: nvgpu: add clk freq controller support

JIRA DNVGPU-127

Add pmu interface structure and command definitions

Change-Id: I5bb84f47057094f55f3adf2c5755416f430aba89
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248207
(cherry picked from commit ad385eb3ce8ffb2d55ae312901c9dcc4e1543b14)
Reviewed-on: http://git-master/r/1267433
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

1 files changed, 43 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h
index d1e5e53e..70f26707 100644
--- a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h
@@ -46,6 +46,7 @@ enum nv_pmu_clk_clkwhich {
 #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE                          0x02
 #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE                          0x03
 #define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT                        0x04
+#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER                 0x05
 
 /*!
 * CLK_DOMAIN BOARDOBJGRP Header structure.  Describes global state about the
@@ -309,6 +310,48 @@ struct nv_pmu_clk_load {
                 struct nv_pmu_clk_load_payload_freq_controllers freq_controllers;
         } payload;
 };
+/* CLK_FREQ_CONTROLLER */
+#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003)
+
+#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO  (0x00000000)
+#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002)
+
+struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32  super;
+        u32 sampling_period_ms;
+        u8 volt_policy_idx;
+};
+
+struct nv_pmu_clk_clk_freq_controller_boardobj_set {
+        struct nv_pmu_boardobj super;
+        u8   controller_id;
+        u8   parts_freq_mode;
+        bool bdisable;
+        u32  clk_domain;
+        s16  freq_cap_noise_unaware_vmin_above;
+        s16  freq_cap_noise_unaware_vmin_below;
+        s16  freq_hyst_pos_mhz;
+        s16  freq_hyst_neg_mhz;
+};
+
+struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set {
+        struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
+        s32 prop_gain;
+        s32 integ_gain;
+        s32 integ_decay;
+        s32 volt_delta_min;
+        s32 volt_delta_max;
+        u8  slowdown_pct_min;
+        bool bpoison;
+};
+
+union nv_pmu_clk_clk_freq_controller_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
+        struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller);
 
 /* CLK CMD ID definitions.  */
 #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET                          (0x00000000)