diff options
author | Supriya <ssharatkumar@nvidia.com> | 2014-10-27 08:01:04 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:56 -0400 |
commit | eb690cb391ca0578a2c086eff5085f16c32f651e (patch) | |
tree | eaa7ba386296c52a3ded108ca53418b5a91cf8ae | |
parent | 8c6a9fd1151299697037d58f33cfa306d8ac5d87 (diff) |
gpu: nvgpu: Changes to support LS sig
Support added to send PMU and FECS signatures
to ACR ucode
Bug 200046413
Change-Id: Ie1babb640be20a697ad4d6dd18bd11161edb263c
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 119 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 88 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 24 |
6 files changed, 224 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 524547e7..b07d0803 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1998,6 +1998,8 @@ void gr_gk20a_load_ctxsw_ucode_header(struct gk20a *g, u64 addr_base, | |||
1998 | 1998 | ||
1999 | /* Write out the actual data */ | 1999 | /* Write out the actual data */ |
2000 | switch (segments->boot_signature) { | 2000 | switch (segments->boot_signature) { |
2001 | case FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED: | ||
2002 | case FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED: | ||
2001 | case FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED: | 2003 | case FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED: |
2002 | case FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED: | 2004 | case FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED: |
2003 | gk20a_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); | 2005 | gk20a_writel(g, reg_offset + gr_fecs_dmemd_r(0), 0); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 7db6bccf..7a4303f7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -304,10 +304,12 @@ struct gk20a_ctxsw_ucode_segments { | |||
304 | /* sums over the ucode files as sequences of u32, computed to the | 304 | /* sums over the ucode files as sequences of u32, computed to the |
305 | * boot_signature field in the structure above */ | 305 | * boot_signature field in the structure above */ |
306 | 306 | ||
307 | #define FALCON_UCODE_SIG_T21X_FECS_WITH_RESERVED 0x9125ab5c | ||
307 | #define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78 | 308 | #define FALCON_UCODE_SIG_T12X_FECS_WITH_RESERVED 0x8a621f78 |
308 | #define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b | 309 | #define FALCON_UCODE_SIG_T12X_FECS_WITHOUT_RESERVED 0x67e5344b |
309 | #define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09f | 310 | #define FALCON_UCODE_SIG_T12X_FECS_OLDER 0x56da09f |
310 | 311 | ||
312 | #define FALCON_UCODE_SIG_T21X_GPCCS_WITH_RESERVED 0x3d3d65e2 | ||
311 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5 | 313 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITH_RESERVED 0x303465d5 |
312 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3 | 314 | #define FALCON_UCODE_SIG_T12X_GPCCS_WITHOUT_RESERVED 0x3fdd33d3 |
313 | #define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877 | 315 | #define FALCON_UCODE_SIG_T12X_GPCCS_OLDER 0x53d7877 |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 0580f19d..3fa7e53c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -155,6 +155,37 @@ static void set_pmu_cmdline_args_falctracedmaidx_v2( | |||
155 | pmu->args_v2.falc_trace_dma_idx = idx; | 155 | pmu->args_v2.falc_trace_dma_idx = idx; |
156 | } | 156 | } |
157 | 157 | ||
158 | static u32 pmu_cmdline_size_v3(struct pmu_gk20a *pmu) | ||
159 | { | ||
160 | return sizeof(struct pmu_cmdline_args_v3); | ||
161 | } | ||
162 | |||
163 | static void set_pmu_cmdline_args_cpufreq_v3(struct pmu_gk20a *pmu, u32 freq) | ||
164 | { | ||
165 | pmu->args_v3.cpu_freq_hz = freq; | ||
166 | } | ||
167 | static void set_pmu_cmdline_args_secure_mode_v3(struct pmu_gk20a *pmu, u32 val) | ||
168 | { | ||
169 | pmu->args_v3.secure_mode = val; | ||
170 | } | ||
171 | |||
172 | static void set_pmu_cmdline_args_falctracesize_v3( | ||
173 | struct pmu_gk20a *pmu, u32 size) | ||
174 | { | ||
175 | pmu->args_v3.falc_trace_size = size; | ||
176 | } | ||
177 | |||
178 | static void set_pmu_cmdline_args_falctracedmabase_v3(struct pmu_gk20a *pmu) | ||
179 | { | ||
180 | pmu->args_v3.falc_trace_dma_base = ((u32)pmu->trace_buf.pmu_va)/0x100; | ||
181 | } | ||
182 | |||
183 | static void set_pmu_cmdline_args_falctracedmaidx_v3( | ||
184 | struct pmu_gk20a *pmu, u32 idx) | ||
185 | { | ||
186 | pmu->args_v3.falc_trace_dma_idx = idx; | ||
187 | } | ||
188 | |||
158 | static void set_pmu_cmdline_args_cpufreq_v1(struct pmu_gk20a *pmu, u32 freq) | 189 | static void set_pmu_cmdline_args_cpufreq_v1(struct pmu_gk20a *pmu, u32 freq) |
159 | { | 190 | { |
160 | pmu->args_v1.cpu_freq_hz = freq; | 191 | pmu->args_v1.cpu_freq_hz = freq; |
@@ -229,6 +260,11 @@ static void set_pmu_cmdline_args_cpufreq_v0(struct pmu_gk20a *pmu, u32 freq) | |||
229 | pmu->args_v0.cpu_freq_hz = freq; | 260 | pmu->args_v0.cpu_freq_hz = freq; |
230 | } | 261 | } |
231 | 262 | ||
263 | static void *get_pmu_cmdline_args_ptr_v3(struct pmu_gk20a *pmu) | ||
264 | { | ||
265 | return (void *)(&pmu->args_v3); | ||
266 | } | ||
267 | |||
232 | static void *get_pmu_cmdline_args_ptr_v2(struct pmu_gk20a *pmu) | 268 | static void *get_pmu_cmdline_args_ptr_v2(struct pmu_gk20a *pmu) |
233 | { | 269 | { |
234 | return (void *)(&pmu->args_v2); | 270 | return (void *)(&pmu->args_v2); |
@@ -661,6 +697,89 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
661 | pmu->remove_support = gk20a_remove_pmu_support; | 697 | pmu->remove_support = gk20a_remove_pmu_support; |
662 | 698 | ||
663 | switch (pmu->desc->app_version) { | 699 | switch (pmu->desc->app_version) { |
700 | case APP_VERSION_GM20B_4: | ||
701 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; | ||
702 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2; | ||
703 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2; | ||
704 | g->ops.pmu_ver.set_perfmon_cntr_valid = | ||
705 | set_perfmon_cntr_valid_v2; | ||
706 | g->ops.pmu_ver.set_perfmon_cntr_index = | ||
707 | set_perfmon_cntr_index_v2; | ||
708 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | ||
709 | set_perfmon_cntr_group_id_v2; | ||
710 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | ||
711 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | ||
712 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | ||
713 | pmu_cmdline_size_v3; | ||
714 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | ||
715 | set_pmu_cmdline_args_cpufreq_v3; | ||
716 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = | ||
717 | set_pmu_cmdline_args_secure_mode_v3; | ||
718 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size = | ||
719 | set_pmu_cmdline_args_falctracesize_v3; | ||
720 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base = | ||
721 | set_pmu_cmdline_args_falctracedmabase_v3; | ||
722 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx = | ||
723 | set_pmu_cmdline_args_falctracedmaidx_v3; | ||
724 | g->ops.pmu_ver.get_pmu_cmdline_args_ptr = | ||
725 | get_pmu_cmdline_args_ptr_v3; | ||
726 | g->ops.pmu_ver.get_pmu_allocation_struct_size = | ||
727 | get_pmu_allocation_size_v1; | ||
728 | g->ops.pmu_ver.set_pmu_allocation_ptr = | ||
729 | set_pmu_allocation_ptr_v1; | ||
730 | g->ops.pmu_ver.pmu_allocation_set_dmem_size = | ||
731 | pmu_allocation_set_dmem_size_v1; | ||
732 | g->ops.pmu_ver.pmu_allocation_get_dmem_size = | ||
733 | pmu_allocation_get_dmem_size_v1; | ||
734 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset = | ||
735 | pmu_allocation_get_dmem_offset_v1; | ||
736 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr = | ||
737 | pmu_allocation_get_dmem_offset_addr_v1; | ||
738 | g->ops.pmu_ver.pmu_allocation_set_dmem_offset = | ||
739 | pmu_allocation_set_dmem_offset_v1; | ||
740 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | ||
741 | get_pmu_init_msg_pmu_queue_params_v1; | ||
742 | g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = | ||
743 | get_pmu_msg_pmu_init_msg_ptr_v1; | ||
744 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = | ||
745 | get_pmu_init_msg_pmu_sw_mg_off_v1; | ||
746 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = | ||
747 | get_pmu_init_msg_pmu_sw_mg_size_v1; | ||
748 | g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = | ||
749 | get_pmu_perfmon_cmd_start_size_v1; | ||
750 | g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = | ||
751 | get_perfmon_cmd_start_offsetofvar_v1; | ||
752 | g->ops.pmu_ver.perfmon_start_set_cmd_type = | ||
753 | perfmon_start_set_cmd_type_v1; | ||
754 | g->ops.pmu_ver.perfmon_start_set_group_id = | ||
755 | perfmon_start_set_group_id_v1; | ||
756 | g->ops.pmu_ver.perfmon_start_set_state_id = | ||
757 | perfmon_start_set_state_id_v1; | ||
758 | g->ops.pmu_ver.perfmon_start_set_flags = | ||
759 | perfmon_start_set_flags_v1; | ||
760 | g->ops.pmu_ver.perfmon_start_get_flags = | ||
761 | perfmon_start_get_flags_v1; | ||
762 | g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size = | ||
763 | get_pmu_perfmon_cmd_init_size_v1; | ||
764 | g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar = | ||
765 | get_perfmon_cmd_init_offsetofvar_v1; | ||
766 | g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer = | ||
767 | perfmon_cmd_init_set_sample_buffer_v1; | ||
768 | g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt = | ||
769 | perfmon_cmd_init_set_dec_cnt_v1; | ||
770 | g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id = | ||
771 | perfmon_cmd_init_set_base_cnt_id_v1; | ||
772 | g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us = | ||
773 | perfmon_cmd_init_set_samp_period_us_v1; | ||
774 | g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt = | ||
775 | perfmon_cmd_init_set_num_cnt_v1; | ||
776 | g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg = | ||
777 | perfmon_cmd_init_set_mov_avg_v1; | ||
778 | g->ops.pmu_ver.get_pmu_seq_in_a_ptr = | ||
779 | get_pmu_sequence_in_alloc_ptr_v1; | ||
780 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = | ||
781 | get_pmu_sequence_out_alloc_ptr_v1; | ||
782 | break; | ||
664 | case APP_VERSION_GM20B_3: | 783 | case APP_VERSION_GM20B_3: |
665 | case APP_VERSION_GM20B_2: | 784 | case APP_VERSION_GM20B_2: |
666 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; | 785 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 823f5484..8b79af95 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -49,6 +49,7 @@ | |||
49 | /* Mapping between AP_CTRLs and Idle counters */ | 49 | /* Mapping between AP_CTRLs and Idle counters */ |
50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | 50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) |
51 | 51 | ||
52 | #define APP_VERSION_GM20B_4 19008461 | ||
52 | #define APP_VERSION_GM20B_3 18935575 | 53 | #define APP_VERSION_GM20B_3 18935575 |
53 | #define APP_VERSION_GM20B_2 18694072 | 54 | #define APP_VERSION_GM20B_2 18694072 |
54 | #define APP_VERSION_GM20B_1 18547257 | 55 | #define APP_VERSION_GM20B_1 18547257 |
@@ -349,6 +350,18 @@ struct pmu_cmdline_args_v2 { | |||
349 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | 350 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ |
350 | }; | 351 | }; |
351 | 352 | ||
353 | struct pmu_cmdline_args_v3 { | ||
354 | u32 reserved; | ||
355 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
356 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | ||
357 | u32 falc_trace_dma_base; /* 256-byte block address */ | ||
358 | u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */ | ||
359 | u8 secure_mode; | ||
360 | u8 raise_priv_sec; /*Raise priv level required for desired | ||
361 | registers*/ | ||
362 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | ||
363 | }; | ||
364 | |||
352 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ | 365 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ |
353 | #define GK20A_PMU_DMEM_BLKSIZE2 8 | 366 | #define GK20A_PMU_DMEM_BLKSIZE2 8 |
354 | 367 | ||
@@ -1174,6 +1187,7 @@ struct pmu_gk20a { | |||
1174 | struct pmu_cmdline_args_v0 args_v0; | 1187 | struct pmu_cmdline_args_v0 args_v0; |
1175 | struct pmu_cmdline_args_v1 args_v1; | 1188 | struct pmu_cmdline_args_v1 args_v1; |
1176 | struct pmu_cmdline_args_v2 args_v2; | 1189 | struct pmu_cmdline_args_v2 args_v2; |
1190 | struct pmu_cmdline_args_v3 args_v3; | ||
1177 | }; | 1191 | }; |
1178 | unsigned long perfmon_events_cnt; | 1192 | unsigned long perfmon_events_cnt; |
1179 | bool perfmon_sampling_enabled; | 1193 | bool perfmon_sampling_enabled; |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index acfcf41b..50b495a6 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -81,7 +81,7 @@ void gm20b_init_secure_pmu(struct gpu_ops *gops) | |||
81 | 81 | ||
82 | int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | 82 | int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) |
83 | { | 83 | { |
84 | const struct firmware *pmu_fw, *pmu_desc; | 84 | const struct firmware *pmu_fw, *pmu_desc, *pmu_sig; |
85 | struct pmu_gk20a *pmu = &g->pmu; | 85 | struct pmu_gk20a *pmu = &g->pmu; |
86 | struct lsf_ucode_desc *lsf_desc; | 86 | struct lsf_ucode_desc *lsf_desc; |
87 | int err; | 87 | int err; |
@@ -89,7 +89,6 @@ int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
89 | pmu_fw = gk20a_request_firmware(g, GM20B_PMU_UCODE_IMAGE); | 89 | pmu_fw = gk20a_request_firmware(g, GM20B_PMU_UCODE_IMAGE); |
90 | if (!pmu_fw) { | 90 | if (!pmu_fw) { |
91 | gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode!!"); | 91 | gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode!!"); |
92 | gm20b_dbg_pmu("requesting PMU ucode in GM20B failed\n"); | ||
93 | return -ENOENT; | 92 | return -ENOENT; |
94 | } | 93 | } |
95 | g->acr.pmu_fw = pmu_fw; | 94 | g->acr.pmu_fw = pmu_fw; |
@@ -99,10 +98,15 @@ int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
99 | pmu_desc = gk20a_request_firmware(g, GM20B_PMU_UCODE_DESC); | 98 | pmu_desc = gk20a_request_firmware(g, GM20B_PMU_UCODE_DESC); |
100 | if (!pmu_desc) { | 99 | if (!pmu_desc) { |
101 | gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!"); | 100 | gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!"); |
102 | gm20b_dbg_pmu("requesting PMU ucode in GM20B failed\n"); | ||
103 | err = -ENOENT; | 101 | err = -ENOENT; |
104 | goto release_img_fw; | 102 | goto release_img_fw; |
105 | } | 103 | } |
104 | pmu_sig = gk20a_request_firmware(g, GM20B_PMU_UCODE_SIG); | ||
105 | if (!pmu_sig) { | ||
106 | gk20a_err(dev_from_gk20a(g), "failed to load pmu sig!!"); | ||
107 | err = -ENOENT; | ||
108 | goto release_desc; | ||
109 | } | ||
106 | pmu->desc = (struct pmu_ucode_desc *)pmu_desc->data; | 110 | pmu->desc = (struct pmu_ucode_desc *)pmu_desc->data; |
107 | pmu->ucode_image = (u32 *)pmu_fw->data; | 111 | pmu->ucode_image = (u32 *)pmu_fw->data; |
108 | g->acr.pmu_desc = pmu_desc; | 112 | g->acr.pmu_desc = pmu_desc; |
@@ -116,8 +120,9 @@ int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
116 | lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc), GFP_KERNEL); | 120 | lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc), GFP_KERNEL); |
117 | if (!lsf_desc) { | 121 | if (!lsf_desc) { |
118 | err = -ENOMEM; | 122 | err = -ENOMEM; |
119 | goto release_desc; | 123 | goto release_sig; |
120 | } | 124 | } |
125 | memcpy(lsf_desc, (void *)pmu_sig->data, sizeof(struct lsf_ucode_desc)); | ||
121 | lsf_desc->falcon_id = LSF_FALCON_ID_PMU; | 126 | lsf_desc->falcon_id = LSF_FALCON_ID_PMU; |
122 | 127 | ||
123 | p_img->desc = pmu->desc; | 128 | p_img->desc = pmu->desc; |
@@ -127,7 +132,10 @@ int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
127 | p_img->header = NULL; | 132 | p_img->header = NULL; |
128 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; | 133 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; |
129 | gm20b_dbg_pmu("requesting PMU ucode in GM20B exit\n"); | 134 | gm20b_dbg_pmu("requesting PMU ucode in GM20B exit\n"); |
135 | release_firmware(pmu_sig); | ||
130 | return 0; | 136 | return 0; |
137 | release_sig: | ||
138 | release_firmware(pmu_sig); | ||
131 | release_desc: | 139 | release_desc: |
132 | release_firmware(pmu_desc); | 140 | release_firmware(pmu_desc); |
133 | release_img_fw: | 141 | release_img_fw: |
@@ -138,41 +146,54 @@ release_img_fw: | |||
138 | int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | 146 | int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) |
139 | { | 147 | { |
140 | struct lsf_ucode_desc *lsf_desc; | 148 | struct lsf_ucode_desc *lsf_desc; |
149 | const struct firmware *fecs_sig; | ||
150 | int err; | ||
141 | 151 | ||
152 | fecs_sig = gk20a_request_firmware(g, GM20B_FECS_UCODE_SIG); | ||
153 | if (!fecs_sig) { | ||
154 | gk20a_err(dev_from_gk20a(g), "failed to load fecs sig"); | ||
155 | return -ENOENT; | ||
156 | } | ||
142 | lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc), GFP_KERNEL); | 157 | lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc), GFP_KERNEL); |
143 | if (!lsf_desc) | 158 | if (!lsf_desc) { |
144 | return -ENOMEM; | 159 | err = -ENOMEM; |
160 | goto rel_sig; | ||
161 | } | ||
162 | memcpy(lsf_desc, (void *)fecs_sig->data, sizeof(struct lsf_ucode_desc)); | ||
145 | lsf_desc->falcon_id = LSF_FALCON_ID_FECS; | 163 | lsf_desc->falcon_id = LSF_FALCON_ID_FECS; |
146 | 164 | ||
147 | p_img->desc = kzalloc(sizeof(struct pmu_ucode_desc), GFP_KERNEL); | 165 | p_img->desc = kzalloc(sizeof(struct pmu_ucode_desc), GFP_KERNEL); |
148 | if (p_img->desc == NULL) { | 166 | if (p_img->desc == NULL) { |
149 | kfree(lsf_desc); | 167 | kfree(lsf_desc); |
150 | return -ENOMEM; | 168 | err = -ENOMEM; |
169 | goto free_lsf_desc; | ||
151 | } | 170 | } |
152 | 171 | ||
153 | p_img->desc->bootloader_start_offset = | 172 | p_img->desc->bootloader_start_offset = |
154 | g->ctxsw_ucode_info.fecs.boot.offset; | 173 | g->ctxsw_ucode_info.fecs.boot.offset; |
155 | p_img->desc->bootloader_size = | 174 | p_img->desc->bootloader_size = |
156 | g->ctxsw_ucode_info.fecs.boot.size; | 175 | ALIGN(g->ctxsw_ucode_info.fecs.boot.size, 256); |
157 | p_img->desc->bootloader_imem_offset = | 176 | p_img->desc->bootloader_imem_offset = |
158 | g->ctxsw_ucode_info.fecs.boot_imem_offset; | 177 | g->ctxsw_ucode_info.fecs.boot_imem_offset; |
159 | p_img->desc->bootloader_entry_point = | 178 | p_img->desc->bootloader_entry_point = |
160 | g->ctxsw_ucode_info.fecs.boot_entry; | 179 | g->ctxsw_ucode_info.fecs.boot_entry; |
161 | 180 | ||
162 | p_img->desc->image_size = g->ctxsw_ucode_info.fecs.boot.size + | 181 | p_img->desc->image_size = |
163 | g->ctxsw_ucode_info.fecs.code.size + | 182 | ALIGN(g->ctxsw_ucode_info.fecs.boot.size, 256) + |
164 | g->ctxsw_ucode_info.fecs.data.size; | 183 | ALIGN(g->ctxsw_ucode_info.fecs.code.size, 256) + |
165 | p_img->desc->app_size = 0; | 184 | ALIGN(g->ctxsw_ucode_info.fecs.data.size, 256); |
166 | p_img->desc->app_start_offset = 0; | 185 | p_img->desc->app_size = ALIGN(g->ctxsw_ucode_info.fecs.code.size, 256) + |
186 | ALIGN(g->ctxsw_ucode_info.fecs.data.size, 256); | ||
187 | p_img->desc->app_start_offset = g->ctxsw_ucode_info.fecs.code.offset; | ||
167 | p_img->desc->app_imem_offset = 0; | 188 | p_img->desc->app_imem_offset = 0; |
168 | p_img->desc->app_imem_entry = 0; | 189 | p_img->desc->app_imem_entry = 0; |
169 | p_img->desc->app_dmem_offset = 0; | 190 | p_img->desc->app_dmem_offset = 0; |
170 | p_img->desc->app_resident_code_offset = | 191 | p_img->desc->app_resident_code_offset = 0; |
171 | g->ctxsw_ucode_info.fecs.code.offset; | ||
172 | p_img->desc->app_resident_code_size = | 192 | p_img->desc->app_resident_code_size = |
173 | g->ctxsw_ucode_info.fecs.code.size; | 193 | g->ctxsw_ucode_info.fecs.code.size; |
174 | p_img->desc->app_resident_data_offset = | 194 | p_img->desc->app_resident_data_offset = |
175 | g->ctxsw_ucode_info.fecs.data.offset; | 195 | g->ctxsw_ucode_info.fecs.data.offset - |
196 | g->ctxsw_ucode_info.fecs.code.offset; | ||
176 | p_img->desc->app_resident_data_size = | 197 | p_img->desc->app_resident_data_size = |
177 | g->ctxsw_ucode_info.fecs.data.size; | 198 | g->ctxsw_ucode_info.fecs.data.size; |
178 | p_img->data = g->ctxsw_ucode_info.surface_desc.cpuva; | 199 | p_img->data = g->ctxsw_ucode_info.surface_desc.cpuva; |
@@ -181,8 +202,14 @@ int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
181 | p_img->fw_ver = NULL; | 202 | p_img->fw_ver = NULL; |
182 | p_img->header = NULL; | 203 | p_img->header = NULL; |
183 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; | 204 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; |
184 | gm20b_dbg_pmu("fecs fw loaded 2\n"); | 205 | gm20b_dbg_pmu("fecs fw loaded\n"); |
206 | release_firmware(fecs_sig); | ||
185 | return 0; | 207 | return 0; |
208 | free_lsf_desc: | ||
209 | kfree(lsf_desc); | ||
210 | rel_sig: | ||
211 | release_firmware(fecs_sig); | ||
212 | return err; | ||
186 | } | 213 | } |
187 | 214 | ||
188 | int prepare_ucode_blob(struct gk20a *g) | 215 | int prepare_ucode_blob(struct gk20a *g) |
@@ -411,7 +438,7 @@ int flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
411 | 438 | ||
412 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); | 439 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); |
413 | struct flcn_bl_dmem_desc *ldr_cfg = | 440 | struct flcn_bl_dmem_desc *ldr_cfg = |
414 | (struct flcn_bl_dmem_desc *)(&p_bl_gen_desc->loader_cfg); | 441 | (struct flcn_bl_dmem_desc *)(&p_bl_gen_desc->bl_dmem_desc); |
415 | u64 addr_base; | 442 | u64 addr_base; |
416 | struct pmu_ucode_desc *desc; | 443 | struct pmu_ucode_desc *desc; |
417 | u64 addr_code, addr_data; | 444 | u64 addr_code, addr_data; |
@@ -580,7 +607,7 @@ static int lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm, | |||
580 | 607 | ||
581 | /* Tag the terminator WPR header with an invalid falcon ID. */ | 608 | /* Tag the terminator WPR header with an invalid falcon ID. */ |
582 | gk20a_mem_wr32(&wpr_hdr[plsfm->managed_flcn_cnt].falcon_id, | 609 | gk20a_mem_wr32(&wpr_hdr[plsfm->managed_flcn_cnt].falcon_id, |
583 | 1, LSF_FALCON_ID_INVALID); | 610 | 0, LSF_FALCON_ID_INVALID); |
584 | } | 611 | } |
585 | return status; | 612 | return status; |
586 | } | 613 | } |
@@ -635,6 +662,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | |||
635 | { | 662 | { |
636 | 663 | ||
637 | struct pmu_gk20a *pmu = &g->pmu; | 664 | struct pmu_gk20a *pmu = &g->pmu; |
665 | u32 full_app_size = 0; | ||
638 | u32 data = 0; | 666 | u32 data = 0; |
639 | 667 | ||
640 | if (pnode->ucode_img.lsf_desc) | 668 | if (pnode->ucode_img.lsf_desc) |
@@ -669,11 +697,30 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | |||
669 | pnode->lsb_header.bl_code_size = ALIGN( | 697 | pnode->lsb_header.bl_code_size = ALIGN( |
670 | pnode->ucode_img.desc->bootloader_size, | 698 | pnode->ucode_img.desc->bootloader_size, |
671 | LSF_BL_CODE_SIZE_ALIGNMENT); | 699 | LSF_BL_CODE_SIZE_ALIGNMENT); |
700 | full_app_size = ALIGN(pnode->ucode_img.desc->app_size, | ||
701 | LSF_BL_CODE_SIZE_ALIGNMENT) + | ||
702 | pnode->lsb_header.bl_code_size; | ||
703 | pnode->lsb_header.ucode_size = ALIGN( | ||
704 | pnode->ucode_img.desc->app_resident_data_offset, | ||
705 | LSF_BL_CODE_SIZE_ALIGNMENT) + | ||
706 | pnode->lsb_header.bl_code_size; | ||
707 | pnode->lsb_header.data_size = full_app_size - | ||
708 | pnode->lsb_header.ucode_size; | ||
672 | /* Though the BL is located at 0th offset of the image, the VA | 709 | /* Though the BL is located at 0th offset of the image, the VA |
673 | is different to make sure that it doesnt collide the actual OS | 710 | is different to make sure that it doesnt collide the actual OS |
674 | VA range */ | 711 | VA range */ |
675 | pnode->lsb_header.bl_imem_off = | 712 | pnode->lsb_header.bl_imem_off = |
676 | pnode->ucode_img.desc->bootloader_imem_offset; | 713 | pnode->ucode_img.desc->bootloader_imem_offset; |
714 | pnode->lsb_header.app_code_off = | ||
715 | pnode->ucode_img.desc->app_start_offset + | ||
716 | pnode->ucode_img.desc->app_resident_code_offset; | ||
717 | pnode->lsb_header.app_code_size = | ||
718 | pnode->ucode_img.desc->app_resident_code_size; | ||
719 | pnode->lsb_header.app_data_off = | ||
720 | pnode->ucode_img.desc->app_start_offset + | ||
721 | pnode->ucode_img.desc->app_resident_data_offset; | ||
722 | pnode->lsb_header.app_data_size = | ||
723 | pnode->ucode_img.desc->app_resident_data_size; | ||
677 | 724 | ||
678 | /* TODO: OBJFLCN should export properties using which the below | 725 | /* TODO: OBJFLCN should export properties using which the below |
679 | flags should be populated.*/ | 726 | flags should be populated.*/ |
@@ -974,7 +1021,8 @@ err_release_acr_fw: | |||
974 | 1021 | ||
975 | u8 pmu_is_debug_mode_en(struct gk20a *g) | 1022 | u8 pmu_is_debug_mode_en(struct gk20a *g) |
976 | { | 1023 | { |
977 | return 1; | 1024 | u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r()); |
1025 | return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat); | ||
978 | } | 1026 | } |
979 | 1027 | ||
980 | /* | 1028 | /* |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 5dddc0b2..5fd5c39b 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -28,6 +28,8 @@ | |||
28 | #define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" | 28 | #define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" |
29 | #define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin" | 29 | #define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin" |
30 | #define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin" | 30 | #define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin" |
31 | #define GM20B_PMU_UCODE_SIG "pmu_sig.bin" | ||
32 | #define GM20B_FECS_UCODE_SIG "fecs_sig.bin" | ||
31 | 33 | ||
32 | #define LSFM_DISABLE_MASK_NONE (0x00000000) /*Disable all LS falcons*/ | 34 | #define LSFM_DISABLE_MASK_NONE (0x00000000) /*Disable all LS falcons*/ |
33 | #define LSFM_DISABLE_MASK_ALL (0xFFFFFFFF) /*Enable all LS falcons*/ | 35 | #define LSFM_DISABLE_MASK_ALL (0xFFFFFFFF) /*Enable all LS falcons*/ |
@@ -60,10 +62,13 @@ | |||
60 | /*! | 62 | /*! |
61 | * Image Status Defines | 63 | * Image Status Defines |
62 | */ | 64 | */ |
63 | #define LSF_IMAGE_STATUS_NONE (0) | 65 | #define LSF_IMAGE_STATUS_NONE (0) |
64 | #define LSF_IMAGE_STATUS_COPY (1) | 66 | #define LSF_IMAGE_STATUS_COPY (1) |
65 | #define LSF_IMAGE_STATUS_VALIDATION (2) | 67 | #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2) |
66 | #define LSF_IMAGE_STATUS_BOOTSTRAP_READY (3) | 68 | #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3) |
69 | #define LSF_IMAGE_STATUS_VALIDATION_DONE (4) | ||
70 | #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5) | ||
71 | #define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6) | ||
67 | 72 | ||
68 | /*LSB header related defines*/ | 73 | /*LSB header related defines*/ |
69 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 | 74 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 |
@@ -156,6 +161,10 @@ struct lsf_lsb_header { | |||
156 | u32 bl_imem_off; | 161 | u32 bl_imem_off; |
157 | u32 bl_data_off; | 162 | u32 bl_data_off; |
158 | u32 bl_data_size; | 163 | u32 bl_data_size; |
164 | u32 app_code_off; | ||
165 | u32 app_code_size; | ||
166 | u32 app_data_off; | ||
167 | u32 app_data_size; | ||
159 | u32 flags; | 168 | u32 flags; |
160 | }; | 169 | }; |
161 | 170 | ||
@@ -178,6 +187,7 @@ struct lsf_lsb_header { | |||
178 | * data_size - Size of data block. Should be multiple of 256B | 187 | * data_size - Size of data block. Should be multiple of 256B |
179 | */ | 188 | */ |
180 | struct flcn_bl_dmem_desc { | 189 | struct flcn_bl_dmem_desc { |
190 | u32 reserved[4]; /*Should be the first element..*/ | ||
181 | u32 signature[4]; /*Should be the first element..*/ | 191 | u32 signature[4]; /*Should be the first element..*/ |
182 | u32 ctx_dma; | 192 | u32 ctx_dma; |
183 | u32 code_dma_base; | 193 | u32 code_dma_base; |
@@ -297,10 +307,14 @@ struct flcn_acr_regions { | |||
297 | * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob | 307 | * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob |
298 | */ | 308 | */ |
299 | struct flcn_acr_desc { | 309 | struct flcn_acr_desc { |
300 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | 310 | union { |
311 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
312 | u32 signatures[4]; | ||
313 | } ucode_reserved_space; | ||
301 | /*Always 1st*/ | 314 | /*Always 1st*/ |
302 | u32 wpr_region_id; | 315 | u32 wpr_region_id; |
303 | u32 wpr_offset; | 316 | u32 wpr_offset; |
317 | u32 mmu_mem_range; | ||
304 | struct flcn_acr_regions regions; | 318 | struct flcn_acr_regions regions; |
305 | u32 nonwpr_ucode_blob_size; | 319 | u32 nonwpr_ucode_blob_size; |
306 | u64 nonwpr_ucode_blob_start; | 320 | u64 nonwpr_ucode_blob_start; |