diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-09-19 22:03:45 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-10-01 16:31:34 -0400 |
commit | e233b0fdcdf19ed6356a31fed04654f2ee103d98 (patch) | |
tree | a8b0612cddb352856468ee417d4ad94e3bc2dd54 | |
parent | 6e97491b007d4231e1934896a423027fda61c4c2 (diff) |
gpu: nvgpu: Commit cb manager at context create
Call commit_cb_manager() at context creation time instead of hardware
initialization. This allows per-channel sizes for buffers.
Bug 1686189
Change-Id: Ie4d08e87f237bc63bac0268128f59d4fe8536c95
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801777
Reviewed-on: http://git-master/r/806181
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 13 |
2 files changed, 3 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 18f00c63..19d9cffc 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -767,7 +767,7 @@ static int gr_gk20a_commit_global_cb_manager(struct gk20a *g, | |||
767 | struct channel_gk20a *c, bool patch) | 767 | struct channel_gk20a *c, bool patch) |
768 | { | 768 | { |
769 | struct gr_gk20a *gr = &g->gr; | 769 | struct gr_gk20a *gr = &g->gr; |
770 | struct channel_ctx_gk20a *ch_ctx = NULL; | 770 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
771 | u32 attrib_offset_in_chunk = 0; | 771 | u32 attrib_offset_in_chunk = 0; |
772 | u32 alpha_offset_in_chunk = 0; | 772 | u32 alpha_offset_in_chunk = 0; |
773 | u32 pd_ab_max_output; | 773 | u32 pd_ab_max_output; |
@@ -777,14 +777,6 @@ static int gr_gk20a_commit_global_cb_manager(struct gk20a *g, | |||
777 | 777 | ||
778 | gk20a_dbg_fn(""); | 778 | gk20a_dbg_fn(""); |
779 | 779 | ||
780 | if (patch) { | ||
781 | int err; | ||
782 | ch_ctx = &c->ch_ctx; | ||
783 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | ||
784 | if (err) | ||
785 | return err; | ||
786 | } | ||
787 | |||
788 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_r(), | 780 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_r(), |
789 | gr_ds_tga_constraintlogic_beta_cbsize_f(gr->attrib_cb_default_size) | | 781 | gr_ds_tga_constraintlogic_beta_cbsize_f(gr->attrib_cb_default_size) | |
790 | gr_ds_tga_constraintlogic_alpha_cbsize_f(gr->alpha_cb_default_size), | 782 | gr_ds_tga_constraintlogic_alpha_cbsize_f(gr->alpha_cb_default_size), |
@@ -831,9 +823,6 @@ static int gr_gk20a_commit_global_cb_manager(struct gk20a *g, | |||
831 | } | 823 | } |
832 | } | 824 | } |
833 | 825 | ||
834 | if (patch) | ||
835 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
836 | |||
837 | return 0; | 826 | return 0; |
838 | } | 827 | } |
839 | 828 | ||
@@ -891,6 +880,7 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g, | |||
891 | 880 | ||
892 | gk20a_dbg_info("attrib cb addr : 0x%016llx", addr); | 881 | gk20a_dbg_info("attrib cb addr : 0x%016llx", addr); |
893 | g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, patch); | 882 | g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, patch); |
883 | g->ops.gr.commit_global_cb_manager(g, c, patch); | ||
894 | 884 | ||
895 | if (patch) | 885 | if (patch) |
896 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | 886 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); |
@@ -4184,7 +4174,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4184 | gr_fe_go_idle_timeout_count_disabled_f()); | 4174 | gr_fe_go_idle_timeout_count_disabled_f()); |
4185 | 4175 | ||
4186 | /* override a few ctx state registers */ | 4176 | /* override a few ctx state registers */ |
4187 | g->ops.gr.commit_global_cb_manager(g, NULL, false); | ||
4188 | gr_gk20a_commit_global_timeslice(g, NULL, false); | 4177 | gr_gk20a_commit_global_timeslice(g, NULL, false); |
4189 | 4178 | ||
4190 | /* floorsweep anything left */ | 4179 | /* floorsweep anything left */ |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index df7f2af9..b8533f46 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -170,7 +170,7 @@ static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, | |||
170 | struct channel_gk20a *c, bool patch) | 170 | struct channel_gk20a *c, bool patch) |
171 | { | 171 | { |
172 | struct gr_gk20a *gr = &g->gr; | 172 | struct gr_gk20a *gr = &g->gr; |
173 | struct channel_ctx_gk20a *ch_ctx = NULL; | 173 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
174 | u32 attrib_offset_in_chunk = 0; | 174 | u32 attrib_offset_in_chunk = 0; |
175 | u32 alpha_offset_in_chunk = 0; | 175 | u32 alpha_offset_in_chunk = 0; |
176 | u32 pd_ab_max_output; | 176 | u32 pd_ab_max_output; |
@@ -180,14 +180,6 @@ static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, | |||
180 | 180 | ||
181 | gk20a_dbg_fn(""); | 181 | gk20a_dbg_fn(""); |
182 | 182 | ||
183 | if (patch) { | ||
184 | int err; | ||
185 | ch_ctx = &c->ch_ctx; | ||
186 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | ||
187 | if (err) | ||
188 | return err; | ||
189 | } | ||
190 | |||
191 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_r(), | 183 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_r(), |
192 | gr_ds_tga_constraintlogic_beta_cbsize_f(gr->attrib_cb_default_size) | | 184 | gr_ds_tga_constraintlogic_beta_cbsize_f(gr->attrib_cb_default_size) | |
193 | gr_ds_tga_constraintlogic_alpha_cbsize_f(gr->alpha_cb_default_size), | 185 | gr_ds_tga_constraintlogic_alpha_cbsize_f(gr->alpha_cb_default_size), |
@@ -247,9 +239,6 @@ static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, | |||
247 | } | 239 | } |
248 | } | 240 | } |
249 | 241 | ||
250 | if (patch) | ||
251 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
252 | |||
253 | return 0; | 242 | return 0; |
254 | } | 243 | } |
255 | 244 | ||