diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-06-23 12:22:33 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:17 -0500 |
commit | e175580d52759c4faa0e05eb728340b31fa7c4d6 (patch) | |
tree | 4fed23d6cce2895e1033458a26ec178c30a993fa | |
parent | 528758f488a8f39c1306d8c17be4799273a94a5d (diff) |
gpu: nvgpu: vgpu: Add CE engine to engine list
Initialize CE engine also for gp10b.
Change-Id: Ibce2f80b523a09fb1345995c03c5430f3b20844f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1170453
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Tested-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c index 34d942c1..23d945fb 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -13,8 +13,36 @@ | |||
13 | 13 | ||
14 | #include "vgpu_fifo_gp10b.h" | 14 | #include "vgpu_fifo_gp10b.h" |
15 | 15 | ||
16 | static int vgpu_gp10b_fifo_init_engine_info(struct fifo_gk20a *f) | ||
17 | { | ||
18 | struct fifo_engine_info_gk20a *gr_info; | ||
19 | struct fifo_engine_info_gk20a *ce_info; | ||
20 | const u32 gr_sw_id = ENGINE_GR_GK20A; | ||
21 | const u32 ce_sw_id = ENGINE_GRCE_GK20A; | ||
22 | |||
23 | gk20a_dbg_fn(""); | ||
24 | |||
25 | f->num_engines = 2; | ||
26 | |||
27 | gr_info = &f->engine_info[0]; | ||
28 | |||
29 | /* FIXME: retrieve this from server */ | ||
30 | gr_info->runlist_id = 0; | ||
31 | gr_info->engine_enum = gr_sw_id; | ||
32 | f->active_engines_list[0] = 0; | ||
33 | |||
34 | ce_info = &f->engine_info[1]; | ||
35 | ce_info->runlist_id = 0; | ||
36 | ce_info->inst_id = 0; | ||
37 | ce_info->engine_enum = ce_sw_id; | ||
38 | f->active_engines_list[1] = 1; | ||
39 | |||
40 | return 0; | ||
41 | } | ||
42 | |||
16 | void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) | 43 | void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) |
17 | { | 44 | { |
18 | /* syncpoint protection not supported yet */ | 45 | /* syncpoint protection not supported yet */ |
46 | gops->fifo.init_engine_info = vgpu_gp10b_fifo_init_engine_info; | ||
19 | gops->fifo.resetup_ramfc = NULL; | 47 | gops->fifo.resetup_ramfc = NULL; |
20 | } | 48 | } |