Revert "gpu: nvgpu: WAR: unbind_channel_verify_status ret val"

This reverts commit a8643b3a99af5011f4e933967f8a09f227ce4949.

Proper resolution is implemented in user space (nvrm_gpu) to idle all channels
of TSG before unbinding a channel from it
And with that we should not see NEXT bit set on channel while unbinding

Hence revert the WAR and again return error if we find NEXT bit set on channel
Also restore the error print

Bug 200327095

Change-Id: Id58e00c4602a4a5c9f65e5ee1329b606f45993d7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585991
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 58a4180f..76995406 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1947,10 +1947,9 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch)
         struct gk20a *g = ch->g;
 
         if (gk20a_fifo_channel_status_is_next(g, ch->chid)) {
-                nvgpu_log(g, gpu_dbg_info,
-                        "Channel %d to be removed from TSG %d has NEXT set!",
+                nvgpu_err(g, "Channel %d to be removed from TSG %d has NEXT set!",
                         ch->chid, ch->tsgid);
-                return 0;
+                return -EINVAL;
         }
 
         if (g->ops.fifo.tsg_verify_status_ctx_reload)