gpu: nvgpu: Remove securegpccs flag from gpu_ops

Replace securegpccs boolean flag in gpu_ops with entry in
common flag system.

The new common flag is NVGPU_SEC_SECUREGPCCS

Jira NVGPU-74

Change-Id: I46430f95063f617531cf0e5aba472051b41f4a9d
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514060
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

9 files changed, 25 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 17a06099..8728c9a7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -993,7 +993,6 @@ struct gpu_ops {
                 void (*isr)(struct gk20a *g);
         } priv_ring;
         bool privsecurity;
-        bool securegpccs;
 };
 
 struct nvgpu_bios_ucode {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index d0c4dec7..cc57b09f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2400,7 +2400,8 @@ static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g)
                 return ret;
         }
 
-        if (g->ops.gr_ctx.use_dma_for_fw_bootstrap || g->ops.securegpccs)
+        if (g->ops.gr_ctx.use_dma_for_fw_bootstrap ||
+                nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS))
                 gk20a_writel(g, gr_fecs_current_ctx_r(),
                         gr_fecs_current_ctx_valid_false_f());
 
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 1bc51a7c..0d69b5da 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -28,6 +28,7 @@
 #include <nvgpu/firmware.h>
 #include <nvgpu/pmu.h>
 #include <nvgpu/falcon.h>
+#include <nvgpu/enabled.h>
 
 #include <nvgpu/linux/dma.h>
 
@@ -267,7 +268,7 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
         struct nvgpu_firmware *gpccs_sig;
         int err;
 
-        if (g->ops.securegpccs == false)
+        if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS))
                 return -ENOENT;
 
         gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0);
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index bd9b627f..5d9cc32c 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -758,7 +758,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
         g->ops.pmu.lsfloadedfalconid = 0;
         if (g->ops.pmu.fecsbootstrapdone) {
                 /* this must be recovery so bootstrap fecs and gpccs */
-                if (!g->ops.securegpccs) {
+                if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
                         gr_gm20b_load_gpccs_with_bootloader(g);
                         err = g->ops.pmu.load_lsfalcon_ucode(g,
                                         (1 << LSF_FALCON_ID_FECS));
@@ -777,7 +777,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
         } else {
                 /* cold boot or rg exit */
                 g->ops.pmu.fecsbootstrapdone = true;
-                if (!g->ops.securegpccs) {
+                if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
                         gr_gm20b_load_gpccs_with_bootloader(g);
                 } else {
                         /* bind WPR VA inst block */
@@ -797,7 +797,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
         }
 
         /*start gpccs */
-        if (g->ops.securegpccs) {
+        if (nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
                 gk20a_writel(g, reg_offset +
                         gr_fecs_cpuctl_alias_r(),
                         gr_gpccs_cpuctl_startcpu_f(1));
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 7415e6c1..01e277ce 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -351,8 +351,9 @@ int gm20b_init_hal(struct gk20a *g)
                 gm20b_ops.chip_init_gpu_characteristics;
         gops->get_litter_value = gm20b_ops.get_litter_value;
 
-        gops->securegpccs = false;
+        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
+
 #ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 gops->privsecurity = 1;
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index dce297bd..929036a3 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -21,6 +21,7 @@
 #include <nvgpu/acr/nvgpu_acr.h>
 #include <nvgpu/firmware.h>
 #include <nvgpu/pmu.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/pmu_gk20a.h"
@@ -286,7 +287,7 @@ int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
         struct nvgpu_firmware *gpccs_sig = NULL;
         int err;
 
-        if (g->ops.securegpccs == false)
+        if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS))
                 return -ENOENT;
 
         switch (ver) {
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 2a661734..80117ede 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -417,7 +417,7 @@ int gp106_init_hal(struct gk20a *g)
         gops->bios_init = gp106_ops.bios_init;
 
         gops->privsecurity = 1;
-        gops->securegpccs = 1;
+        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
 
         g->bootstrap_owner = LSF_FALCON_ID_SEC2;
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 177a7c9f..818949f0 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -369,36 +369,36 @@ int gp10b_init_hal(struct gk20a *g)
 #ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 gops->privsecurity = 0;
-                gops->securegpccs = 0;
+                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         } else if (g->is_virtual) {
                 gops->privsecurity = 1;
-                gops->securegpccs = 1;
+                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
         } else {
                 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
                 if (val) {
                         gops->privsecurity = 1;
-                        gops->securegpccs =1;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
                 } else {
                         gk20a_dbg_info("priv security is disabled in HW");
                         gops->privsecurity = 0;
-                        gops->securegpccs = 0;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
                 }
         }
 #else
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 gk20a_dbg_info("running simulator with PRIV security disabled");
                 gops->privsecurity = 0;
-                gops->securegpccs = 0;
+                __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         } else {
                 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
                 if (val) {
                         gk20a_dbg_info("priv security is not supported but enabled");
                         gops->privsecurity = 1;
-                        gops->securegpccs =1;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
                         return -EPERM;
                 } else {
                         gops->privsecurity = 0;
-                        gops->securegpccs = 0;
+                        __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
                 }
         }
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index 6fa7dcfa..7d495f48 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -38,6 +38,12 @@ struct gk20a;
 #define NVGPU_MM_UNIFIED_MEMORY                 18
 
 /*
+ * Security flags
+ */
+
+#define NVGPU_SEC_SECUREGPCCS                   32
+
+/*
  * PMU flags.
  */
 /* perfmon enabled or disabled for PMU */