diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-02-01 06:28:05 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-09 16:44:31 -0500 |
commit | de2dfd0c1ee5249f39ff58ce81cbdad0a5ad8cca (patch) | |
tree | e023ac24c4c63997d0f0cbb74a4558e302d78eb4 | |
parent | 2caa3a9361bb0c9e08a7bb788387a379c73bc848 (diff) |
gpu: nvgpu: PMU perfmon interface header reorg
Moved perfmon interface from
pmu_api.h & pmu_gk20a.h to gpmuif_perfmon.h
header files
gpmuif_perfmon.h - PMU Command/Message Interfaces
PERFMON
Jira NVGPU-19
Change-Id: I983f89f0f6ec3b889d975178fb1405f166b7d1b9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297262
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_api.h | 137 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h | 178 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 1 |
4 files changed, 179 insertions, 170 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index 6284f2f9..4d249524 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h | |||
@@ -17,143 +17,6 @@ | |||
17 | #include <nvgpu/flcnif_cmn.h> | 17 | #include <nvgpu/flcnif_cmn.h> |
18 | #include "pmuif/gpmuif_pg_rppg.h" | 18 | #include "pmuif/gpmuif_pg_rppg.h" |
19 | 19 | ||
20 | /*---------------------------------------------------------*/ | ||
21 | |||
22 | /*perfmon task defines*/ | ||
23 | enum pmu_perfmon_cmd_start_fields { | ||
24 | COUNTER_ALLOC | ||
25 | }; | ||
26 | |||
27 | enum { | ||
28 | PMU_PERFMON_CMD_ID_START = 0, | ||
29 | PMU_PERFMON_CMD_ID_STOP = 1, | ||
30 | PMU_PERFMON_CMD_ID_INIT = 2 | ||
31 | }; | ||
32 | |||
33 | struct pmu_perfmon_cmd_start_v3 { | ||
34 | u8 cmd_type; | ||
35 | u8 group_id; | ||
36 | u8 state_id; | ||
37 | u8 flags; | ||
38 | struct pmu_allocation_v3 counter_alloc; | ||
39 | }; | ||
40 | |||
41 | struct pmu_perfmon_cmd_start_v2 { | ||
42 | u8 cmd_type; | ||
43 | u8 group_id; | ||
44 | u8 state_id; | ||
45 | u8 flags; | ||
46 | struct pmu_allocation_v2 counter_alloc; | ||
47 | }; | ||
48 | |||
49 | struct pmu_perfmon_cmd_start_v1 { | ||
50 | u8 cmd_type; | ||
51 | u8 group_id; | ||
52 | u8 state_id; | ||
53 | u8 flags; | ||
54 | struct pmu_allocation_v1 counter_alloc; | ||
55 | }; | ||
56 | |||
57 | struct pmu_perfmon_cmd_start_v0 { | ||
58 | u8 cmd_type; | ||
59 | u8 group_id; | ||
60 | u8 state_id; | ||
61 | u8 flags; | ||
62 | struct pmu_allocation_v0 counter_alloc; | ||
63 | }; | ||
64 | |||
65 | struct pmu_perfmon_cmd_stop { | ||
66 | u8 cmd_type; | ||
67 | }; | ||
68 | |||
69 | struct pmu_perfmon_cmd_init_v3 { | ||
70 | u8 cmd_type; | ||
71 | u8 to_decrease_count; | ||
72 | u8 base_counter_id; | ||
73 | u32 sample_period_us; | ||
74 | struct pmu_allocation_v3 counter_alloc; | ||
75 | u8 num_counters; | ||
76 | u8 samples_in_moving_avg; | ||
77 | u16 sample_buffer; | ||
78 | }; | ||
79 | |||
80 | struct pmu_perfmon_cmd_init_v2 { | ||
81 | u8 cmd_type; | ||
82 | u8 to_decrease_count; | ||
83 | u8 base_counter_id; | ||
84 | u32 sample_period_us; | ||
85 | struct pmu_allocation_v2 counter_alloc; | ||
86 | u8 num_counters; | ||
87 | u8 samples_in_moving_avg; | ||
88 | u16 sample_buffer; | ||
89 | }; | ||
90 | |||
91 | struct pmu_perfmon_cmd_init_v1 { | ||
92 | u8 cmd_type; | ||
93 | u8 to_decrease_count; | ||
94 | u8 base_counter_id; | ||
95 | u32 sample_period_us; | ||
96 | struct pmu_allocation_v1 counter_alloc; | ||
97 | u8 num_counters; | ||
98 | u8 samples_in_moving_avg; | ||
99 | u16 sample_buffer; | ||
100 | }; | ||
101 | |||
102 | struct pmu_perfmon_cmd_init_v0 { | ||
103 | u8 cmd_type; | ||
104 | u8 to_decrease_count; | ||
105 | u8 base_counter_id; | ||
106 | u32 sample_period_us; | ||
107 | struct pmu_allocation_v0 counter_alloc; | ||
108 | u8 num_counters; | ||
109 | u8 samples_in_moving_avg; | ||
110 | u16 sample_buffer; | ||
111 | }; | ||
112 | |||
113 | struct pmu_perfmon_cmd { | ||
114 | union { | ||
115 | u8 cmd_type; | ||
116 | struct pmu_perfmon_cmd_start_v0 start_v0; | ||
117 | struct pmu_perfmon_cmd_start_v1 start_v1; | ||
118 | struct pmu_perfmon_cmd_start_v2 start_v2; | ||
119 | struct pmu_perfmon_cmd_start_v3 start_v3; | ||
120 | struct pmu_perfmon_cmd_stop stop; | ||
121 | struct pmu_perfmon_cmd_init_v0 init_v0; | ||
122 | struct pmu_perfmon_cmd_init_v1 init_v1; | ||
123 | struct pmu_perfmon_cmd_init_v2 init_v2; | ||
124 | struct pmu_perfmon_cmd_init_v3 init_v3; | ||
125 | }; | ||
126 | }; | ||
127 | |||
128 | struct pmu_zbc_cmd { | ||
129 | u8 cmd_type; | ||
130 | u8 pad; | ||
131 | u16 entry_mask; | ||
132 | }; | ||
133 | |||
134 | /* PERFMON MSG */ | ||
135 | enum { | ||
136 | PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, | ||
137 | PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, | ||
138 | PMU_PERFMON_MSG_ID_INIT_EVENT = 2, | ||
139 | PMU_PERFMON_MSG_ID_ACK = 3 | ||
140 | }; | ||
141 | |||
142 | struct pmu_perfmon_msg_generic { | ||
143 | u8 msg_type; | ||
144 | u8 state_id; | ||
145 | u8 group_id; | ||
146 | u8 data; | ||
147 | }; | ||
148 | |||
149 | struct pmu_perfmon_msg { | ||
150 | union { | ||
151 | u8 msg_type; | ||
152 | struct pmu_perfmon_msg_generic gen; | ||
153 | }; | ||
154 | }; | ||
155 | |||
156 | /*---------------------------------------------------------*/ | ||
157 | /* ACR Commands/Message structures */ | 20 | /* ACR Commands/Message structures */ |
158 | 21 | ||
159 | enum { | 22 | enum { |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index b4a69720..87246f42 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -134,39 +134,6 @@ struct pmu_ucode_desc_v1 { | |||
134 | */ | 134 | */ |
135 | #define ACR_ERROR_INVALID_TRANSCFG_SETUP (0xAC120001) | 135 | #define ACR_ERROR_INVALID_TRANSCFG_SETUP (0xAC120001) |
136 | 136 | ||
137 | /* PERFMON */ | ||
138 | #define PMU_DOMAIN_GROUP_PSTATE 0 | ||
139 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 | ||
140 | #define PMU_DOMAIN_GROUP_NUM 2 | ||
141 | |||
142 | /* TBD: smart strategy */ | ||
143 | #define PMU_PERFMON_PCT_TO_INC 58 | ||
144 | #define PMU_PERFMON_PCT_TO_DEC 23 | ||
145 | |||
146 | struct pmu_perfmon_counter_v0 { | ||
147 | u8 index; | ||
148 | u8 flags; | ||
149 | u8 group_id; | ||
150 | u8 valid; | ||
151 | u16 upper_threshold; /* units of 0.01% */ | ||
152 | u16 lower_threshold; /* units of 0.01% */ | ||
153 | }; | ||
154 | |||
155 | struct pmu_perfmon_counter_v2 { | ||
156 | u8 index; | ||
157 | u8 flags; | ||
158 | u8 group_id; | ||
159 | u8 valid; | ||
160 | u16 upper_threshold; /* units of 0.01% */ | ||
161 | u16 lower_threshold; /* units of 0.01% */ | ||
162 | u32 scale; | ||
163 | }; | ||
164 | |||
165 | #define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) | ||
166 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) | ||
167 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) | ||
168 | |||
169 | |||
170 | #define PMU_PGENG_GR_BUFFER_IDX_INIT (0) | 137 | #define PMU_PGENG_GR_BUFFER_IDX_INIT (0) |
171 | #define PMU_PGENG_GR_BUFFER_IDX_ZBC (1) | 138 | #define PMU_PGENG_GR_BUFFER_IDX_ZBC (1) |
172 | #define PMU_PGENG_GR_BUFFER_IDX_FECS (2) | 139 | #define PMU_PGENG_GR_BUFFER_IDX_FECS (2) |
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h new file mode 100644 index 00000000..098d0305 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h | |||
@@ -0,0 +1,178 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFPERFMON_H_ | ||
14 | #define _GPMUIFPERFMON_H_ | ||
15 | |||
16 | /*perfmon task defines*/ | ||
17 | |||
18 | #define PMU_DOMAIN_GROUP_PSTATE 0 | ||
19 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 | ||
20 | #define PMU_DOMAIN_GROUP_NUM 2 | ||
21 | |||
22 | #define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) | ||
23 | #define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) | ||
24 | #define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) | ||
25 | |||
26 | enum pmu_perfmon_cmd_start_fields { | ||
27 | COUNTER_ALLOC | ||
28 | }; | ||
29 | |||
30 | enum { | ||
31 | PMU_PERFMON_CMD_ID_START = 0, | ||
32 | PMU_PERFMON_CMD_ID_STOP = 1, | ||
33 | PMU_PERFMON_CMD_ID_INIT = 2 | ||
34 | }; | ||
35 | |||
36 | struct pmu_perfmon_counter_v0 { | ||
37 | u8 index; | ||
38 | u8 flags; | ||
39 | u8 group_id; | ||
40 | u8 valid; | ||
41 | u16 upper_threshold; /* units of 0.01% */ | ||
42 | u16 lower_threshold; /* units of 0.01% */ | ||
43 | }; | ||
44 | |||
45 | struct pmu_perfmon_counter_v2 { | ||
46 | u8 index; | ||
47 | u8 flags; | ||
48 | u8 group_id; | ||
49 | u8 valid; | ||
50 | u16 upper_threshold; /* units of 0.01% */ | ||
51 | u16 lower_threshold; /* units of 0.01% */ | ||
52 | u32 scale; | ||
53 | }; | ||
54 | |||
55 | struct pmu_perfmon_cmd_start_v3 { | ||
56 | u8 cmd_type; | ||
57 | u8 group_id; | ||
58 | u8 state_id; | ||
59 | u8 flags; | ||
60 | struct pmu_allocation_v3 counter_alloc; | ||
61 | }; | ||
62 | |||
63 | struct pmu_perfmon_cmd_start_v2 { | ||
64 | u8 cmd_type; | ||
65 | u8 group_id; | ||
66 | u8 state_id; | ||
67 | u8 flags; | ||
68 | struct pmu_allocation_v2 counter_alloc; | ||
69 | }; | ||
70 | |||
71 | struct pmu_perfmon_cmd_start_v1 { | ||
72 | u8 cmd_type; | ||
73 | u8 group_id; | ||
74 | u8 state_id; | ||
75 | u8 flags; | ||
76 | struct pmu_allocation_v1 counter_alloc; | ||
77 | }; | ||
78 | |||
79 | struct pmu_perfmon_cmd_start_v0 { | ||
80 | u8 cmd_type; | ||
81 | u8 group_id; | ||
82 | u8 state_id; | ||
83 | u8 flags; | ||
84 | struct pmu_allocation_v0 counter_alloc; | ||
85 | }; | ||
86 | |||
87 | struct pmu_perfmon_cmd_stop { | ||
88 | u8 cmd_type; | ||
89 | }; | ||
90 | |||
91 | struct pmu_perfmon_cmd_init_v3 { | ||
92 | u8 cmd_type; | ||
93 | u8 to_decrease_count; | ||
94 | u8 base_counter_id; | ||
95 | u32 sample_period_us; | ||
96 | struct pmu_allocation_v3 counter_alloc; | ||
97 | u8 num_counters; | ||
98 | u8 samples_in_moving_avg; | ||
99 | u16 sample_buffer; | ||
100 | }; | ||
101 | |||
102 | struct pmu_perfmon_cmd_init_v2 { | ||
103 | u8 cmd_type; | ||
104 | u8 to_decrease_count; | ||
105 | u8 base_counter_id; | ||
106 | u32 sample_period_us; | ||
107 | struct pmu_allocation_v2 counter_alloc; | ||
108 | u8 num_counters; | ||
109 | u8 samples_in_moving_avg; | ||
110 | u16 sample_buffer; | ||
111 | }; | ||
112 | |||
113 | struct pmu_perfmon_cmd_init_v1 { | ||
114 | u8 cmd_type; | ||
115 | u8 to_decrease_count; | ||
116 | u8 base_counter_id; | ||
117 | u32 sample_period_us; | ||
118 | struct pmu_allocation_v1 counter_alloc; | ||
119 | u8 num_counters; | ||
120 | u8 samples_in_moving_avg; | ||
121 | u16 sample_buffer; | ||
122 | }; | ||
123 | |||
124 | struct pmu_perfmon_cmd_init_v0 { | ||
125 | u8 cmd_type; | ||
126 | u8 to_decrease_count; | ||
127 | u8 base_counter_id; | ||
128 | u32 sample_period_us; | ||
129 | struct pmu_allocation_v0 counter_alloc; | ||
130 | u8 num_counters; | ||
131 | u8 samples_in_moving_avg; | ||
132 | u16 sample_buffer; | ||
133 | }; | ||
134 | |||
135 | struct pmu_perfmon_cmd { | ||
136 | union { | ||
137 | u8 cmd_type; | ||
138 | struct pmu_perfmon_cmd_start_v0 start_v0; | ||
139 | struct pmu_perfmon_cmd_start_v1 start_v1; | ||
140 | struct pmu_perfmon_cmd_start_v2 start_v2; | ||
141 | struct pmu_perfmon_cmd_start_v3 start_v3; | ||
142 | struct pmu_perfmon_cmd_stop stop; | ||
143 | struct pmu_perfmon_cmd_init_v0 init_v0; | ||
144 | struct pmu_perfmon_cmd_init_v1 init_v1; | ||
145 | struct pmu_perfmon_cmd_init_v2 init_v2; | ||
146 | struct pmu_perfmon_cmd_init_v3 init_v3; | ||
147 | }; | ||
148 | }; | ||
149 | |||
150 | struct pmu_zbc_cmd { | ||
151 | u8 cmd_type; | ||
152 | u8 pad; | ||
153 | u16 entry_mask; | ||
154 | }; | ||
155 | |||
156 | /* PERFMON MSG */ | ||
157 | enum { | ||
158 | PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, | ||
159 | PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, | ||
160 | PMU_PERFMON_MSG_ID_INIT_EVENT = 2, | ||
161 | PMU_PERFMON_MSG_ID_ACK = 3 | ||
162 | }; | ||
163 | |||
164 | struct pmu_perfmon_msg_generic { | ||
165 | u8 msg_type; | ||
166 | u8 state_id; | ||
167 | u8 group_id; | ||
168 | u8 data; | ||
169 | }; | ||
170 | |||
171 | struct pmu_perfmon_msg { | ||
172 | union { | ||
173 | u8 msg_type; | ||
174 | struct pmu_perfmon_msg_generic gen; | ||
175 | }; | ||
176 | }; | ||
177 | |||
178 | #endif /* _GPMUIFPERFMON_H_ */ | ||
diff --git a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h index 2ed8d61b..f99d4e9e 100644 --- a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h +++ b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | |||
@@ -19,6 +19,7 @@ | |||
19 | #include "gpmuif_pmu.h" | 19 | #include "gpmuif_pmu.h" |
20 | #include "gpmuif_ap.h" | 20 | #include "gpmuif_ap.h" |
21 | #include "gpmuif_pg.h" | 21 | #include "gpmuif_pg.h" |
22 | #include "gpmuif_perfmon.h" | ||
22 | #include "gpmuifboardobj.h" | 23 | #include "gpmuifboardobj.h" |
23 | #include "gpmuifclk.h" | 24 | #include "gpmuifclk.h" |
24 | #include "gpmuifperf.h" | 25 | #include "gpmuifperf.h" |