diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2015-09-21 18:02:37 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-09-30 11:29:13 -0400 |
commit | dab594ac13e5ca76d09a9ab383c35ad67c1444ef (patch) | |
tree | 44098f9e26af1ba2f9812bcf16dabe8c6fd3ec8e | |
parent | b1cd94025bcd51a82e15eb314ab30e4418372c7f (diff) |
gpu: nvgpu: ELPG init & statistics update
- Required init param to start elpg
- change in statistics dump
Bug 1684939
Change-Id: I26dca52079f08b8962e9cb758831910207610220
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/802456
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/806179
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 55 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 2 |
4 files changed, 59 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 207239d1..a5e130cb 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -392,6 +392,11 @@ struct gpu_ops { | |||
392 | int (*init_wpr_region)(struct gk20a *g); | 392 | int (*init_wpr_region)(struct gk20a *g); |
393 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); | 393 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); |
394 | void (*write_dmatrfbase)(struct gk20a *g, u32 addr); | 394 | void (*write_dmatrfbase)(struct gk20a *g, u32 addr); |
395 | void (*pmu_elpg_statistics)(struct gk20a *g, | ||
396 | u32 *ingating_time, u32 *ungating_time, | ||
397 | u32 *gating_cnt); | ||
398 | int (*pmu_pg_grinit_param)(struct gk20a *g, | ||
399 | u8 grfeaturemask); | ||
395 | u32 lspmuwprinitdone; | 400 | u32 lspmuwprinitdone; |
396 | u32 lsfloadedfalconid; | 401 | u32 lsfloadedfalconid; |
397 | bool fecsbootstrapdone; | 402 | bool fecsbootstrapdone; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 0328e100..4d459ef4 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2769,6 +2769,8 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2769 | gops->pmu.init_wpr_region = NULL; | 2769 | gops->pmu.init_wpr_region = NULL; |
2770 | gops->pmu.load_lsfalcon_ucode = NULL; | 2770 | gops->pmu.load_lsfalcon_ucode = NULL; |
2771 | gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; | 2771 | gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; |
2772 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | ||
2773 | gops->pmu.pmu_pg_grinit_param = NULL; | ||
2772 | } | 2774 | } |
2773 | 2775 | ||
2774 | int gk20a_init_pmu_support(struct gk20a *g) | 2776 | int gk20a_init_pmu_support(struct gk20a *g) |
@@ -2884,6 +2886,10 @@ static int pmu_init_powergating(struct gk20a *g) | |||
2884 | 2886 | ||
2885 | gk20a_gr_wait_initialized(g); | 2887 | gk20a_gr_wait_initialized(g); |
2886 | 2888 | ||
2889 | if (g->ops.pmu.pmu_pg_grinit_param) | ||
2890 | g->ops.pmu.pmu_pg_grinit_param(g, | ||
2891 | PMU_PG_FEATURE_GR_POWER_GATING_ENABLED); | ||
2892 | |||
2887 | /* init ELPG */ | 2893 | /* init ELPG */ |
2888 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 2894 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
2889 | cmd.hdr.unit_id = PMU_UNIT_PG; | 2895 | cmd.hdr.unit_id = PMU_UNIT_PG; |
@@ -4241,11 +4247,24 @@ void gk20a_pmu_reset_load_counters(struct gk20a *g) | |||
4241 | gk20a_idle(g->dev); | 4247 | gk20a_idle(g->dev); |
4242 | } | 4248 | } |
4243 | 4249 | ||
4250 | void gk20a_pmu_elpg_statistics(struct gk20a *g, | ||
4251 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) | ||
4252 | { | ||
4253 | struct pmu_gk20a *pmu = &g->pmu; | ||
4254 | struct pmu_pg_stats stats; | ||
4255 | |||
4256 | pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, | ||
4257 | (u8 *)&stats, sizeof(struct pmu_pg_stats), 0); | ||
4258 | |||
4259 | *ingating_time = stats.pg_ingating_time_us; | ||
4260 | *ungating_time = stats.pg_ungating_time_us; | ||
4261 | *gating_cnt = stats.pg_gating_cnt; | ||
4262 | } | ||
4263 | |||
4244 | static int gk20a_pmu_get_elpg_residency_gating(struct gk20a *g, | 4264 | static int gk20a_pmu_get_elpg_residency_gating(struct gk20a *g, |
4245 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) | 4265 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) |
4246 | { | 4266 | { |
4247 | struct pmu_gk20a *pmu = &g->pmu; | 4267 | struct pmu_gk20a *pmu = &g->pmu; |
4248 | struct pmu_pg_stats stats; | ||
4249 | 4268 | ||
4250 | if (!pmu->initialized) { | 4269 | if (!pmu->initialized) { |
4251 | *ingating_time = 0; | 4270 | *ingating_time = 0; |
@@ -4254,12 +4273,8 @@ static int gk20a_pmu_get_elpg_residency_gating(struct gk20a *g, | |||
4254 | return 0; | 4273 | return 0; |
4255 | } | 4274 | } |
4256 | 4275 | ||
4257 | pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, | 4276 | g->ops.pmu.pmu_elpg_statistics(g, ingating_time, |
4258 | (u8 *)&stats, sizeof(struct pmu_pg_stats), 0); | 4277 | ungating_time, gating_cnt); |
4259 | |||
4260 | *ingating_time = stats.pg_ingating_time_us; | ||
4261 | *ungating_time = stats.pg_ungating_time_us; | ||
4262 | *gating_cnt = stats.pg_gating_cnt; | ||
4263 | 4278 | ||
4264 | return 0; | 4279 | return 0; |
4265 | } | 4280 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index bbfcf4ee..683c1dfc 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -680,6 +680,8 @@ enum { | |||
680 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | 680 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, |
681 | }; | 681 | }; |
682 | 682 | ||
683 | #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 | ||
684 | |||
683 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) | 685 | #define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) |
684 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) | 686 | #define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) |
685 | 687 | ||
@@ -1135,31 +1137,31 @@ struct pmu_sequence { | |||
1135 | }; | 1137 | }; |
1136 | 1138 | ||
1137 | struct pmu_pg_stats_v1 { | 1139 | struct pmu_pg_stats_v1 { |
1138 | /* Number of time PMU successfully engaged sleep state */ | 1140 | /* Number of time PMU successfully engaged sleep state */ |
1139 | u32 entryCount; | 1141 | u32 entry_count; |
1140 | /* Number of time PMU exit sleep state */ | 1142 | /* Number of time PMU exit sleep state */ |
1141 | u32 exitCount; | 1143 | u32 exit_count; |
1142 | /* Number of time PMU aborted in entry sequence */ | 1144 | /* Number of time PMU aborted in entry sequence */ |
1143 | u32 abortCount; | 1145 | u32 abort_count; |
1144 | /* | 1146 | /* |
1145 | * Time for which GPU was neither in Sleep state not | 1147 | * Time for which GPU was neither in Sleep state not |
1146 | * executing sleep sequence. | 1148 | * executing sleep sequence. |
1147 | * */ | 1149 | * */ |
1148 | u32 poweredUpTimeUs; | 1150 | u32 poweredup_timeus; |
1149 | /* Entry and exit latency of current sleep cycle */ | 1151 | /* Entry and exit latency of current sleep cycle */ |
1150 | u32 entryLatencyUs; | 1152 | u32 entry_latency_us; |
1151 | u32 exitLatencyUs; | 1153 | u32 exitlatencyus; |
1152 | /* Resident time for current sleep cycle. */ | 1154 | /* Resident time for current sleep cycle. */ |
1153 | u32 residentTimeUs; | 1155 | u32 resident_timeus; |
1154 | /* Rolling average entry and exit latencies */ | 1156 | /* Rolling average entry and exit latencies */ |
1155 | u32 entryLatencyAvgUs; | 1157 | u32 entrylatency_avgus; |
1156 | u32 exitLatencyAvgUs; | 1158 | u32 exitlatency_avgus; |
1157 | /* Max entry and exit latencies */ | 1159 | /* Max entry and exit latencies */ |
1158 | u32 entryLatencyMaxUs; | 1160 | u32 entrylatency_maxus; |
1159 | u32 exitLatencyMaxUs; | 1161 | u32 exitlatency_maxus; |
1160 | /* Total time spent in sleep and non-sleep state */ | 1162 | /* Total time spent in sleep and non-sleep state */ |
1161 | u32 totalSleepTimeUs; | 1163 | u32 total_sleep_timeus; |
1162 | u32 totalNonSleepTimeUs; | 1164 | u32 total_nonsleep_timeus; |
1163 | }; | 1165 | }; |
1164 | 1166 | ||
1165 | struct pmu_pg_stats { | 1167 | struct pmu_pg_stats { |
@@ -1369,4 +1371,7 @@ int pmu_wait_message_cond(struct pmu_gk20a *pmu, u32 timeout, | |||
1369 | u32 *var, u32 val); | 1371 | u32 *var, u32 val); |
1370 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | 1372 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, |
1371 | void *param, u32 handle, u32 status); | 1373 | void *param, u32 handle, u32 status); |
1374 | void gk20a_pmu_elpg_statistics(struct gk20a *g, | ||
1375 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); | ||
1376 | |||
1372 | #endif /*__PMU_GK20A_H__*/ | 1377 | #endif /*__PMU_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 9cf9cb26..4123e32a 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -306,4 +306,6 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) | |||
306 | gops->pmu.lspmuwprinitdone = 0; | 306 | gops->pmu.lspmuwprinitdone = 0; |
307 | gops->pmu.fecsbootstrapdone = false; | 307 | gops->pmu.fecsbootstrapdone = false; |
308 | gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; | 308 | gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; |
309 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | ||
310 | gops->pmu.pmu_pg_grinit_param = NULL; | ||
309 | } | 311 | } |