diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-04-19 07:27:49 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-09 16:16:29 -0400 |
commit | d868b654419cfa096f563c9281a2a5cc067c23db (patch) | |
tree | a11fc30ab435c6e2a4c54b97455d3f5c177ad507 | |
parent | f14152c081d94710dbde843b8dcd9b3981afb831 (diff) |
gpu: nvgpu: separate IOCTL to set preemption mode
Add separate IOCTL NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE
to allow setting preemption modes from UMD
Define preemption modes in nvgpu.h and use them everywhere
Remove mode definitions from mm_gk20a.h
Also, we support setting only one preemption mode in a channel
But it is possible to have multiple preemption modes (one from
graphics and one from compute) set simultaneously
Hence, update struct gr_ctx_desc to include two separate
preemption modes (graphics_preempt_mode and compute_preempt_mode)
API NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE also supports
setting two separate preemption modes i.e. one for graphics
and one for compute
Make necessary changes in code to support two preemption
modes
Bug 1646259
Change-Id: Ia1dea19e609ba8cc0de2f39ab6c0c4cd6b0a752c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1131805
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 4 | ||||
-rw-r--r-- | include/trace/events/gk20a.h | 47 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 14 |
8 files changed, 89 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 189ec330..990972e4 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -3208,6 +3208,23 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3208 | 3208 | ||
3209 | trace_gk20a_channel_set_timeslice(GK20A_TP_ARGS_SCHED(ch)); | 3209 | trace_gk20a_channel_set_timeslice(GK20A_TP_ARGS_SCHED(ch)); |
3210 | break; | 3210 | break; |
3211 | case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE: | ||
3212 | if (ch->g->ops.gr.set_preemption_mode) { | ||
3213 | err = gk20a_busy(dev); | ||
3214 | if (err) { | ||
3215 | dev_err(dev, | ||
3216 | "%s: failed to host gk20a for ioctl cmd: 0x%x", | ||
3217 | __func__, cmd); | ||
3218 | break; | ||
3219 | } | ||
3220 | err = ch->g->ops.gr.set_preemption_mode(ch, | ||
3221 | ((struct nvgpu_preemption_mode_args *)buf)->graphics_preempt_mode, | ||
3222 | ((struct nvgpu_preemption_mode_args *)buf)->compute_preempt_mode); | ||
3223 | gk20a_idle(dev); | ||
3224 | } else { | ||
3225 | err = -EINVAL; | ||
3226 | } | ||
3227 | break; | ||
3211 | default: | 3228 | default: |
3212 | dev_dbg(dev, "unrecognized ioctl cmd: 0x%x", cmd); | 3229 | dev_dbg(dev, "unrecognized ioctl cmd: 0x%x", cmd); |
3213 | err = -ENOTTY; | 3230 | err = -ENOTTY; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index eccea4d4..dc3debf2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2599,7 +2599,7 @@ static int gk20a_fifo_sched_debugfs_seq_show( | |||
2599 | runlist = &f->runlist_info[runlist_id]; | 2599 | runlist = &f->runlist_info[runlist_id]; |
2600 | 2600 | ||
2601 | if (ch == f->channel) { | 2601 | if (ch == f->channel) { |
2602 | seq_puts(s, "chid tsgid pid timeslice timeout interleave preempt\n"); | 2602 | seq_puts(s, "chid tsgid pid timeslice timeout interleave graphics_preempt compute_preempt\n"); |
2603 | seq_puts(s, " (usecs) (msecs)\n"); | 2603 | seq_puts(s, " (usecs) (msecs)\n"); |
2604 | ret = 0; | 2604 | ret = 0; |
2605 | } | 2605 | } |
@@ -2611,15 +2611,15 @@ static int gk20a_fifo_sched_debugfs_seq_show( | |||
2611 | if (gk20a_is_channel_marked_as_tsg(ch)) | 2611 | if (gk20a_is_channel_marked_as_tsg(ch)) |
2612 | tsg = &f->tsg[ch->tsgid]; | 2612 | tsg = &f->tsg[ch->tsgid]; |
2613 | 2613 | ||
2614 | seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d\n", | 2614 | seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d %-8d\n", |
2615 | ch->hw_chid, | 2615 | ch->hw_chid, |
2616 | ch->tsgid, | 2616 | ch->tsgid, |
2617 | ch->pid, | 2617 | ch->pid, |
2618 | tsg ? tsg->timeslice_us : ch->timeslice_us, | 2618 | tsg ? tsg->timeslice_us : ch->timeslice_us, |
2619 | ch->timeout_ms_max, | 2619 | ch->timeout_ms_max, |
2620 | ch->interleave_level, | 2620 | ch->interleave_level, |
2621 | ch->ch_ctx.gr_ctx ? | 2621 | ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->graphics_preempt_mode : -1, |
2622 | ch->ch_ctx.gr_ctx->preempt_mode : -1); | 2622 | ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->compute_preempt_mode : -1); |
2623 | gk20a_channel_put(ch); | 2623 | gk20a_channel_put(ch); |
2624 | } | 2624 | } |
2625 | return 0; | 2625 | return 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ebc18d5d..64e410db 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -254,6 +254,9 @@ struct gpu_ops { | |||
254 | int (*suspend_contexts)(struct gk20a *g, | 254 | int (*suspend_contexts)(struct gk20a *g, |
255 | struct dbg_session_gk20a *dbg_s, | 255 | struct dbg_session_gk20a *dbg_s, |
256 | int *ctx_resident_ch_fd); | 256 | int *ctx_resident_ch_fd); |
257 | int (*set_preemption_mode)(struct channel_gk20a *ch, | ||
258 | u32 graphics_preempt_mode, | ||
259 | u32 compute_preempt_mode); | ||
257 | } gr; | 260 | } gr; |
258 | const char *name; | 261 | const char *name; |
259 | struct { | 262 | struct { |
@@ -1098,7 +1101,9 @@ static inline struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) | |||
1098 | tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, \ | 1101 | tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, \ |
1099 | ch->timeout_ms_max, \ | 1102 | ch->timeout_ms_max, \ |
1100 | gk20a_fifo_interleave_level_name(ch->interleave_level), \ | 1103 | gk20a_fifo_interleave_level_name(ch->interleave_level), \ |
1101 | gr_gk20a_preempt_mode_name(ch->ch_ctx.gr_ctx ? \ | 1104 | gr_gk20a_graphics_preempt_mode_name(ch->ch_ctx.gr_ctx ? \ |
1102 | ch->ch_ctx.gr_ctx->preempt_mode : 0) | 1105 | ch->ch_ctx.gr_ctx->graphics_preempt_mode : 0), \ |
1106 | gr_gk20a_compute_preempt_mode_name(ch->ch_ctx.gr_ctx ? \ | ||
1107 | ch->ch_ctx.gr_ctx->compute_preempt_mode : 0) | ||
1103 | 1108 | ||
1104 | #endif /* GK20A_H */ | 1109 | #endif /* GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 24123eea..10997c17 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -628,18 +628,23 @@ int gr_gk20a_resume_contexts(struct gk20a *g, | |||
628 | struct dbg_session_gk20a *dbg_s, | 628 | struct dbg_session_gk20a *dbg_s, |
629 | int *ctx_resident_ch_fd); | 629 | int *ctx_resident_ch_fd); |
630 | 630 | ||
631 | #define NVGPU_GR_PREEMPTION_MODE_WFI 0 | 631 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) |
632 | #define NVGPU_GR_PREEMPTION_MODE_CTA 2 | ||
633 | |||
634 | static inline const char *gr_gk20a_preempt_mode_name(u32 preempt_mode) | ||
635 | { | 632 | { |
636 | switch (preempt_mode) { | 633 | switch (graphics_preempt_mode) { |
637 | case NVGPU_GR_PREEMPTION_MODE_WFI: | 634 | case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI: |
638 | return "WFI"; | 635 | return "WFI"; |
636 | default: | ||
637 | return "?"; | ||
638 | } | ||
639 | } | ||
639 | 640 | ||
640 | case NVGPU_GR_PREEMPTION_MODE_CTA: | 641 | static inline const char *gr_gk20a_compute_preempt_mode_name(u32 compute_preempt_mode) |
642 | { | ||
643 | switch (compute_preempt_mode) { | ||
644 | case NVGPU_COMPUTE_PREEMPTION_MODE_WFI: | ||
645 | return "WFI"; | ||
646 | case NVGPU_COMPUTE_PREEMPTION_MODE_CTA: | ||
641 | return "CTA"; | 647 | return "CTA"; |
642 | |||
643 | default: | 648 | default: |
644 | return "?"; | 649 | return "?"; |
645 | } | 650 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 29f32d8f..7fa0b7fb 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -94,7 +94,8 @@ struct gr_ctx_buffer_desc { | |||
94 | struct gr_ctx_desc { | 94 | struct gr_ctx_desc { |
95 | struct mem_desc mem; | 95 | struct mem_desc mem; |
96 | 96 | ||
97 | int preempt_mode; | 97 | int graphics_preempt_mode; |
98 | int compute_preempt_mode; | ||
98 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 99 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC |
99 | struct gr_ctx_desc_t18x t18x; | 100 | struct gr_ctx_desc_t18x t18x; |
100 | #endif | 101 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 35bbe70c..dbe30f00 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -824,7 +824,7 @@ static int gr_gm20b_alloc_gr_ctx(struct gk20a *g, | |||
824 | return err; | 824 | return err; |
825 | 825 | ||
826 | if (class == MAXWELL_COMPUTE_B) | 826 | if (class == MAXWELL_COMPUTE_B) |
827 | (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; | 827 | (*gr_ctx)->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CTA; |
828 | 828 | ||
829 | gk20a_dbg_fn("done"); | 829 | gk20a_dbg_fn("done"); |
830 | 830 | ||
@@ -841,7 +841,7 @@ static void gr_gm20b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
841 | 841 | ||
842 | gk20a_dbg_fn(""); | 842 | gk20a_dbg_fn(""); |
843 | 843 | ||
844 | if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CTA) { | 844 | if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CTA) { |
845 | gk20a_dbg_info("CTA: %x", cta_preempt_option); | 845 | gk20a_dbg_info("CTA: %x", cta_preempt_option); |
846 | gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_preemption_options_o(), 0, | 846 | gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_preemption_options_o(), 0, |
847 | cta_preempt_option); | 847 | cta_preempt_option); |
diff --git a/include/trace/events/gk20a.h b/include/trace/events/gk20a.h index fc5cb872..ba71dda2 100644 --- a/include/trace/events/gk20a.h +++ b/include/trace/events/gk20a.h | |||
@@ -192,9 +192,11 @@ DEFINE_EVENT(gk20a_channel_getput, gk20a_channel_put_nofree, | |||
192 | 192 | ||
193 | DECLARE_EVENT_CLASS(gk20a_channel_sched_params, | 193 | DECLARE_EVENT_CLASS(gk20a_channel_sched_params, |
194 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, | 194 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, |
195 | u32 timeout, const char *interleave, const char *preempt_mode), | 195 | u32 timeout, const char *interleave, |
196 | const char *graphics_preempt_mode, | ||
197 | const char *compute_preempt_mode), | ||
196 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, | 198 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, |
197 | interleave, preempt_mode), | 199 | interleave, graphics_preempt_mode, compute_preempt_mode), |
198 | TP_STRUCT__entry( | 200 | TP_STRUCT__entry( |
199 | __field(int, chid) | 201 | __field(int, chid) |
200 | __field(int, tsgid) | 202 | __field(int, tsgid) |
@@ -202,7 +204,8 @@ DECLARE_EVENT_CLASS(gk20a_channel_sched_params, | |||
202 | __field(u32, timeslice) | 204 | __field(u32, timeslice) |
203 | __field(u32, timeout) | 205 | __field(u32, timeout) |
204 | __field(const char *, interleave) /* no need to copy */ | 206 | __field(const char *, interleave) /* no need to copy */ |
205 | __field(const char *, preempt_mode) /* no need to copy */ | 207 | __field(const char *, graphics_preempt_mode) /* no need to copy */ |
208 | __field(const char *, compute_preempt_mode) /* no need to copy */ | ||
206 | ), | 209 | ), |
207 | TP_fast_assign( | 210 | TP_fast_assign( |
208 | __entry->chid = chid; | 211 | __entry->chid = chid; |
@@ -211,47 +214,59 @@ DECLARE_EVENT_CLASS(gk20a_channel_sched_params, | |||
211 | __entry->timeslice = timeslice; | 214 | __entry->timeslice = timeslice; |
212 | __entry->timeout = timeout; | 215 | __entry->timeout = timeout; |
213 | __entry->interleave = interleave; | 216 | __entry->interleave = interleave; |
214 | __entry->preempt_mode = preempt_mode; | 217 | __entry->graphics_preempt_mode = graphics_preempt_mode; |
218 | __entry->compute_preempt_mode = compute_preempt_mode; | ||
215 | ), | 219 | ), |
216 | TP_printk("chid=%d tsgid=%d pid=%d timeslice=%u timeout=%u interleave=%s preempt=%s", | 220 | TP_printk("chid=%d tsgid=%d pid=%d timeslice=%u timeout=%u interleave=%s graphics_preempt=%s compute_preempt=%s", |
217 | __entry->chid, __entry->tsgid, __entry->pid, | 221 | __entry->chid, __entry->tsgid, __entry->pid, |
218 | __entry->timeslice, __entry->timeout, | 222 | __entry->timeslice, __entry->timeout, |
219 | __entry->interleave, __entry->preempt_mode) | 223 | __entry->interleave, __entry->graphics_preempt_mode, |
224 | __entry->compute_preempt_mode) | ||
220 | ); | 225 | ); |
221 | 226 | ||
222 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_sched_defaults, | 227 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_sched_defaults, |
223 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, | 228 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, |
224 | u32 timeout, const char *interleave, const char *preempt_mode), | 229 | u32 timeout, const char *interleave, |
230 | const char *graphics_preempt_mode, | ||
231 | const char *compute_preempt_mode), | ||
225 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, | 232 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, |
226 | interleave, preempt_mode) | 233 | interleave, graphics_preempt_mode, compute_preempt_mode) |
227 | ); | 234 | ); |
228 | 235 | ||
229 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_priority, | 236 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_priority, |
230 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, | 237 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, |
231 | u32 timeout, const char *interleave, const char *preempt_mode), | 238 | u32 timeout, const char *interleave, |
239 | const char *graphics_preempt_mode, | ||
240 | const char *compute_preempt_mode), | ||
232 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, | 241 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, |
233 | interleave, preempt_mode) | 242 | interleave, graphics_preempt_mode, compute_preempt_mode) |
234 | ); | 243 | ); |
235 | 244 | ||
236 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_runlist_interleave, | 245 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_runlist_interleave, |
237 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, | 246 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, |
238 | u32 timeout, const char *interleave, const char *preempt_mode), | 247 | u32 timeout, const char *interleave, |
248 | const char *graphics_preempt_mode, | ||
249 | const char *compute_preempt_mode), | ||
239 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, | 250 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, |
240 | interleave, preempt_mode) | 251 | interleave, graphics_preempt_mode, compute_preempt_mode) |
241 | ); | 252 | ); |
242 | 253 | ||
243 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_timeslice, | 254 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_timeslice, |
244 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, | 255 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, |
245 | u32 timeout, const char *interleave, const char *preempt_mode), | 256 | u32 timeout, const char *interleave, |
257 | const char *graphics_preempt_mode, | ||
258 | const char *compute_preempt_mode), | ||
246 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, | 259 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, |
247 | interleave, preempt_mode) | 260 | interleave, graphics_preempt_mode, compute_preempt_mode) |
248 | ); | 261 | ); |
249 | 262 | ||
250 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_timeout, | 263 | DEFINE_EVENT(gk20a_channel_sched_params, gk20a_channel_set_timeout, |
251 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, | 264 | TP_PROTO(int chid, int tsgid, pid_t pid, u32 timeslice, |
252 | u32 timeout, const char *interleave, const char *preempt_mode), | 265 | u32 timeout, const char *interleave, |
266 | const char *graphics_preempt_mode, | ||
267 | const char *compute_preempt_mode), | ||
253 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, | 268 | TP_ARGS(chid, tsgid, pid, timeslice, timeout, |
254 | interleave, preempt_mode) | 269 | interleave, graphics_preempt_mode, compute_preempt_mode) |
255 | ); | 270 | ); |
256 | 271 | ||
257 | TRACE_EVENT(gk20a_push_cmdbuf, | 272 | TRACE_EVENT(gk20a_push_cmdbuf, |
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index b8bd21f2..8ebe8d06 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -999,6 +999,16 @@ struct nvgpu_event_id_ctrl_args { | |||
999 | 999 | ||
1000 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1 | 1000 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1 |
1001 | 1001 | ||
1002 | struct nvgpu_preemption_mode_args { | ||
1003 | /* only one should be enabled at a time */ | ||
1004 | #define NVGPU_GRAPHICS_PREEMPTION_MODE_WFI BIT(0) | ||
1005 | __u32 graphics_preempt_mode; /* in */ | ||
1006 | |||
1007 | /* only one should be enabled at a time */ | ||
1008 | #define NVGPU_COMPUTE_PREEMPTION_MODE_WFI BIT(0) | ||
1009 | #define NVGPU_COMPUTE_PREEMPTION_MODE_CTA BIT(1) | ||
1010 | __u32 compute_preempt_mode; /* in */ | ||
1011 | }; | ||
1002 | 1012 | ||
1003 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ | 1013 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ |
1004 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) | 1014 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) |
@@ -1046,9 +1056,11 @@ struct nvgpu_event_id_ctrl_args { | |||
1046 | _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args) | 1056 | _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args) |
1047 | #define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \ | 1057 | #define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \ |
1048 | _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args) | 1058 | _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args) |
1059 | #define NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE \ | ||
1060 | _IOW(NVGPU_IOCTL_MAGIC, 122, struct nvgpu_preemption_mode_args) | ||
1049 | 1061 | ||
1050 | #define NVGPU_IOCTL_CHANNEL_LAST \ | 1062 | #define NVGPU_IOCTL_CHANNEL_LAST \ |
1051 | _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_TIMESLICE) | 1063 | _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE) |
1052 | #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args) | 1064 | #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args) |
1053 | 1065 | ||
1054 | /* | 1066 | /* |