diff options
author | Seema Khowala <seemaj@nvidia.com> | 2016-07-08 19:12:44 -0400 |
---|---|---|
committer | Seshendra Gadagottu <sgadagottu@nvidia.com> | 2016-07-27 17:32:54 -0400 |
commit | d64e2015147c4dc48c0d3b8d6ee612dd8addf04c (patch) | |
tree | 68753a49ca7da2264ff007c675b1dfa32f6da3bd | |
parent | 9ca4c6b596fe50c652907193bb167ee29c208b4b (diff) |
gpu: nvgpu: add check for is_fmodel
is_fmodel flag will be set in gk20a_probe().
Updated code for is_fmodel check, instead of
check for supported simulated platforms.
Bug 1735760
Change-Id: I7cbac2196130fe5ce4c1a910504879e6948c13da
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177869
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_common.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 3 |
11 files changed, 51 insertions, 26 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index a886fd3f..e9ba644c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1483,6 +1483,9 @@ static int gk20a_probe(struct platform_device *dev) | |||
1483 | return -ENODATA; | 1483 | return -ENODATA; |
1484 | } | 1484 | } |
1485 | 1485 | ||
1486 | if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) | ||
1487 | platform->is_fmodel = true; | ||
1488 | |||
1486 | gk20a_dbg_fn(""); | 1489 | gk20a_dbg_fn(""); |
1487 | 1490 | ||
1488 | platform_set_drvdata(dev, platform); | 1491 | platform_set_drvdata(dev, platform); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index 81ac341f..5b76eee2 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -430,7 +430,9 @@ done: | |||
430 | 430 | ||
431 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr) | 431 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr) |
432 | { | 432 | { |
433 | if (tegra_platform_is_linsim()) | 433 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
434 | |||
435 | if (platform->is_fmodel) | ||
434 | return gr_gk20a_init_ctx_vars_sim(g, gr); | 436 | return gr_gk20a_init_ctx_vars_sim(g, gr); |
435 | else | 437 | else |
436 | return gr_gk20a_init_ctx_vars_fw(g, gr); | 438 | return gr_gk20a_init_ctx_vars_fw(g, gr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6fc52ad0..979f69ba 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -372,8 +372,9 @@ static int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long end_jiffies, | |||
372 | { | 372 | { |
373 | u32 val; | 373 | u32 val; |
374 | u32 delay = expect_delay; | 374 | u32 delay = expect_delay; |
375 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
375 | 376 | ||
376 | if (tegra_platform_is_linsim()) | 377 | if (platform->is_fmodel) |
377 | return 0; | 378 | return 0; |
378 | 379 | ||
379 | gk20a_dbg_fn(""); | 380 | gk20a_dbg_fn(""); |
@@ -1491,6 +1492,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1491 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | 1492 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); |
1492 | u32 last_method_data = 0; | 1493 | u32 last_method_data = 0; |
1493 | int retries = FE_PWR_MODE_TIMEOUT_MAX / FE_PWR_MODE_TIMEOUT_DEFAULT; | 1494 | int retries = FE_PWR_MODE_TIMEOUT_MAX / FE_PWR_MODE_TIMEOUT_DEFAULT; |
1495 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1494 | 1496 | ||
1495 | gk20a_dbg_fn(""); | 1497 | gk20a_dbg_fn(""); |
1496 | 1498 | ||
@@ -1502,7 +1504,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1502 | if (gr->ctx_vars.golden_image_initialized) | 1504 | if (gr->ctx_vars.golden_image_initialized) |
1503 | goto clean_up; | 1505 | goto clean_up; |
1504 | 1506 | ||
1505 | if (!tegra_platform_is_linsim()) { | 1507 | if (!platform->is_fmodel) { |
1506 | gk20a_writel(g, gr_fe_pwr_mode_r(), | 1508 | gk20a_writel(g, gr_fe_pwr_mode_r(), |
1507 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); | 1509 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); |
1508 | do { | 1510 | do { |
@@ -1542,7 +1544,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1542 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); | 1544 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); |
1543 | udelay(10); | 1545 | udelay(10); |
1544 | 1546 | ||
1545 | if (!tegra_platform_is_linsim()) { | 1547 | if (!platform->is_fmodel) { |
1546 | gk20a_writel(g, gr_fe_pwr_mode_r(), | 1548 | gk20a_writel(g, gr_fe_pwr_mode_r(), |
1547 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); | 1549 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); |
1548 | 1550 | ||
@@ -1903,6 +1905,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1903 | u32 v, data; | 1905 | u32 v, data; |
1904 | int ret = 0; | 1906 | int ret = 0; |
1905 | struct mem_desc *mem = &ch_ctx->gr_ctx->mem; | 1907 | struct mem_desc *mem = &ch_ctx->gr_ctx->mem; |
1908 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1906 | 1909 | ||
1907 | gk20a_dbg_fn(""); | 1910 | gk20a_dbg_fn(""); |
1908 | 1911 | ||
@@ -1990,7 +1993,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1990 | 1993 | ||
1991 | gk20a_mem_end(g, mem); | 1994 | gk20a_mem_end(g, mem); |
1992 | 1995 | ||
1993 | if (tegra_platform_is_linsim()) { | 1996 | if (platform->is_fmodel) { |
1994 | u32 mdata = fecs_current_ctx_data(g, &c->inst_block); | 1997 | u32 mdata = fecs_current_ctx_data(g, &c->inst_block); |
1995 | 1998 | ||
1996 | ret = gr_gk20a_submit_fecs_method_op(g, | 1999 | ret = gr_gk20a_submit_fecs_method_op(g, |
@@ -2416,10 +2419,11 @@ static void gr_gk20a_load_falcon_with_bootloader(struct gk20a *g) | |||
2416 | int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) | 2419 | int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) |
2417 | { | 2420 | { |
2418 | int err; | 2421 | int err; |
2422 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
2419 | 2423 | ||
2420 | gk20a_dbg_fn(""); | 2424 | gk20a_dbg_fn(""); |
2421 | 2425 | ||
2422 | if (tegra_platform_is_linsim()) { | 2426 | if (platform->is_fmodel) { |
2423 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), | 2427 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), |
2424 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); | 2428 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); |
2425 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), | 2429 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), |
@@ -4211,6 +4215,7 @@ void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) | |||
4211 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | 4215 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) |
4212 | { | 4216 | { |
4213 | u32 gate_ctrl, idle_filter; | 4217 | u32 gate_ctrl, idle_filter; |
4218 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
4214 | 4219 | ||
4215 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); | 4220 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); |
4216 | 4221 | ||
@@ -4239,7 +4244,7 @@ void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | |||
4239 | "invalid elcg mode %d", mode); | 4244 | "invalid elcg mode %d", mode); |
4240 | } | 4245 | } |
4241 | 4246 | ||
4242 | if (tegra_platform_is_linsim()) { | 4247 | if (platform->is_fmodel) { |
4243 | gate_ctrl = set_field(gate_ctrl, | 4248 | gate_ctrl = set_field(gate_ctrl, |
4244 | therm_gate_ctrl_eng_delay_after_m(), | 4249 | therm_gate_ctrl_eng_delay_after_m(), |
4245 | therm_gate_ctrl_eng_delay_after_f(4)); | 4250 | therm_gate_ctrl_eng_delay_after_f(4)); |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c index 45607154..5795fe91 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_common.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GK20A Graphics | 4 | * GK20A Graphics |
5 | * | 5 | * |
6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms and conditions of the GNU General Public License, | 9 | * under the terms and conditions of the GNU General Public License, |
@@ -92,8 +92,9 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | |||
92 | u64 compbit_base_post_multiply64; | 92 | u64 compbit_base_post_multiply64; |
93 | u64 compbit_store_iova; | 93 | u64 compbit_store_iova; |
94 | u64 compbit_base_post_divide64; | 94 | u64 compbit_base_post_divide64; |
95 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
95 | 96 | ||
96 | if (tegra_platform_is_linsim()) | 97 | if (platform->is_fmodel) |
97 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | 98 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); |
98 | else | 99 | else |
99 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | 100 | compbit_store_iova = g->ops.mm.get_iova_addr(g, |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index c891a80b..a81ed66c 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <trace/events/gk20a.h> | 20 | #include <trace/events/gk20a.h> |
21 | 21 | ||
22 | #include "hw_ltc_gk20a.h" | 22 | #include "hw_ltc_gk20a.h" |
23 | #include "gk20a.h" | ||
23 | 24 | ||
24 | #include "ltc_common.c" | 25 | #include "ltc_common.c" |
25 | 26 | ||
@@ -45,6 +46,7 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
45 | u32 compbit_backing_size; | 46 | u32 compbit_backing_size; |
46 | 47 | ||
47 | int err; | 48 | int err; |
49 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
48 | 50 | ||
49 | gk20a_dbg_fn(""); | 51 | gk20a_dbg_fn(""); |
50 | 52 | ||
@@ -78,7 +80,7 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
78 | gk20a_dbg_info("max comptag lines : %d", | 80 | gk20a_dbg_info("max comptag lines : %d", |
79 | max_comptag_lines); | 81 | max_comptag_lines); |
80 | 82 | ||
81 | if (tegra_platform_is_linsim()) | 83 | if (platform->is_fmodel) |
82 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | 84 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); |
83 | else | 85 | else |
84 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | 86 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 6de7425b..16ff8ee8 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -1023,10 +1023,11 @@ static int alloc_gmmu_pages(struct vm_gk20a *vm, u32 order, | |||
1023 | u32 num_pages = 1 << order; | 1023 | u32 num_pages = 1 << order; |
1024 | u32 len = num_pages * PAGE_SIZE; | 1024 | u32 len = num_pages * PAGE_SIZE; |
1025 | int err; | 1025 | int err; |
1026 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1026 | 1027 | ||
1027 | gk20a_dbg_fn(""); | 1028 | gk20a_dbg_fn(""); |
1028 | 1029 | ||
1029 | if (tegra_platform_is_linsim()) | 1030 | if (platform->is_fmodel) |
1030 | return alloc_gmmu_phys_pages(vm, order, entry); | 1031 | return alloc_gmmu_phys_pages(vm, order, entry); |
1031 | 1032 | ||
1032 | /* | 1033 | /* |
@@ -1052,13 +1053,14 @@ void free_gmmu_pages(struct vm_gk20a *vm, | |||
1052 | struct gk20a_mm_entry *entry) | 1053 | struct gk20a_mm_entry *entry) |
1053 | { | 1054 | { |
1054 | struct gk20a *g = gk20a_from_vm(vm); | 1055 | struct gk20a *g = gk20a_from_vm(vm); |
1056 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1055 | 1057 | ||
1056 | gk20a_dbg_fn(""); | 1058 | gk20a_dbg_fn(""); |
1057 | 1059 | ||
1058 | if (!entry->mem.size) | 1060 | if (!entry->mem.size) |
1059 | return; | 1061 | return; |
1060 | 1062 | ||
1061 | if (tegra_platform_is_linsim()) { | 1063 | if (platform->is_fmodel) { |
1062 | free_gmmu_phys_pages(vm, entry); | 1064 | free_gmmu_phys_pages(vm, entry); |
1063 | return; | 1065 | return; |
1064 | } | 1066 | } |
@@ -1076,9 +1078,11 @@ void free_gmmu_pages(struct vm_gk20a *vm, | |||
1076 | 1078 | ||
1077 | int map_gmmu_pages(struct gk20a *g, struct gk20a_mm_entry *entry) | 1079 | int map_gmmu_pages(struct gk20a *g, struct gk20a_mm_entry *entry) |
1078 | { | 1080 | { |
1081 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1082 | |||
1079 | gk20a_dbg_fn(""); | 1083 | gk20a_dbg_fn(""); |
1080 | 1084 | ||
1081 | if (tegra_platform_is_linsim()) | 1085 | if (platform->is_fmodel) |
1082 | return map_gmmu_phys_pages(entry); | 1086 | return map_gmmu_phys_pages(entry); |
1083 | 1087 | ||
1084 | if (IS_ENABLED(CONFIG_ARM64)) { | 1088 | if (IS_ENABLED(CONFIG_ARM64)) { |
@@ -1100,9 +1104,11 @@ int map_gmmu_pages(struct gk20a *g, struct gk20a_mm_entry *entry) | |||
1100 | 1104 | ||
1101 | void unmap_gmmu_pages(struct gk20a *g, struct gk20a_mm_entry *entry) | 1105 | void unmap_gmmu_pages(struct gk20a *g, struct gk20a_mm_entry *entry) |
1102 | { | 1106 | { |
1107 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1108 | |||
1103 | gk20a_dbg_fn(""); | 1109 | gk20a_dbg_fn(""); |
1104 | 1110 | ||
1105 | if (tegra_platform_is_linsim()) { | 1111 | if (platform->is_fmodel) { |
1106 | unmap_gmmu_phys_pages(entry); | 1112 | unmap_gmmu_phys_pages(entry); |
1107 | return; | 1113 | return; |
1108 | } | 1114 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c index 745d963c..819c50a4 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c | |||
@@ -83,7 +83,7 @@ int gk20a_tegra_secure_page_alloc(struct device *dev) | |||
83 | dma_addr_t iova; | 83 | dma_addr_t iova; |
84 | size_t size = PAGE_SIZE; | 84 | size_t size = PAGE_SIZE; |
85 | 85 | ||
86 | if (tegra_platform_is_linsim()) | 86 | if (platform->is_fmodel) |
87 | return -EINVAL; | 87 | return -EINVAL; |
88 | 88 | ||
89 | (void)dma_alloc_attrs(&tegra_vpr_dev, size, &iova, | 89 | (void)dma_alloc_attrs(&tegra_vpr_dev, size, &iova, |
@@ -314,7 +314,7 @@ static bool gk20a_tegra_is_railgated(struct device *dev) | |||
314 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 314 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
315 | bool ret = false; | 315 | bool ret = false; |
316 | 316 | ||
317 | if (!tegra_platform_is_linsim()) | 317 | if (!(platform->is_fmodel)) |
318 | ret = !tegra_dvfs_is_rail_up(platform->gpu_rail); | 318 | ret = !tegra_dvfs_is_rail_up(platform->gpu_rail); |
319 | 319 | ||
320 | return ret; | 320 | return ret; |
@@ -331,7 +331,7 @@ static int gk20a_tegra_railgate(struct device *dev) | |||
331 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 331 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
332 | int ret = 0; | 332 | int ret = 0; |
333 | 333 | ||
334 | if (tegra_platform_is_linsim() || | 334 | if (platform->is_fmodel || |
335 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) | 335 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) |
336 | return 0; | 336 | return 0; |
337 | 337 | ||
@@ -383,7 +383,7 @@ static int gm20b_tegra_railgate(struct device *dev) | |||
383 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 383 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
384 | int ret = 0; | 384 | int ret = 0; |
385 | 385 | ||
386 | if (tegra_platform_is_linsim() || | 386 | if (platform->is_fmodel || |
387 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) | 387 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) |
388 | return 0; | 388 | return 0; |
389 | 389 | ||
@@ -439,7 +439,7 @@ static int gk20a_tegra_unrailgate(struct device *dev) | |||
439 | int ret = 0; | 439 | int ret = 0; |
440 | bool first = false; | 440 | bool first = false; |
441 | 441 | ||
442 | if (tegra_platform_is_linsim()) | 442 | if (platform->is_fmodel) |
443 | return 0; | 443 | return 0; |
444 | 444 | ||
445 | if (!platform->gpu_rail) { | 445 | if (!platform->gpu_rail) { |
@@ -510,7 +510,7 @@ static int gm20b_tegra_unrailgate(struct device *dev) | |||
510 | int ret = 0; | 510 | int ret = 0; |
511 | bool first = false; | 511 | bool first = false; |
512 | 512 | ||
513 | if (tegra_platform_is_linsim()) | 513 | if (platform->is_fmodel) |
514 | return 0; | 514 | return 0; |
515 | 515 | ||
516 | if (!platform->gpu_rail) { | 516 | if (!platform->gpu_rail) { |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index cad74359..f812383f 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -25,7 +25,9 @@ | |||
25 | 25 | ||
26 | void gk20a_reset_priv_ring(struct gk20a *g) | 26 | void gk20a_reset_priv_ring(struct gk20a *g) |
27 | { | 27 | { |
28 | if (tegra_platform_is_linsim()) | 28 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
29 | |||
30 | if (platform->is_fmodel) | ||
29 | return; | 31 | return; |
30 | 32 | ||
31 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) | 33 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) |
@@ -50,8 +52,9 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
50 | u32 status0, status1; | 52 | u32 status0, status1; |
51 | u32 cmd; | 53 | u32 cmd; |
52 | s32 retry = 100; | 54 | s32 retry = 100; |
55 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
53 | 56 | ||
54 | if (tegra_platform_is_linsim()) | 57 | if (platform->is_fmodel) |
55 | return; | 58 | return; |
56 | 59 | ||
57 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 60 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index d57b0fb5..c2aa64ba 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -709,10 +709,11 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
709 | u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - | 709 | u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - |
710 | gr_fecs_falcon_hwcfg_r(); | 710 | gr_fecs_falcon_hwcfg_r(); |
711 | u8 falcon_id_mask = 0; | 711 | u8 falcon_id_mask = 0; |
712 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
712 | 713 | ||
713 | gk20a_dbg_fn(""); | 714 | gk20a_dbg_fn(""); |
714 | 715 | ||
715 | if (tegra_platform_is_linsim()) { | 716 | if (platform->is_fmodel) { |
716 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), | 717 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), |
717 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); | 718 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); |
718 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), | 719 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 57cafd38..caf6a2eb 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -177,11 +177,12 @@ int gm20b_init_hal(struct gk20a *g) | |||
177 | { | 177 | { |
178 | struct gpu_ops *gops = &g->ops; | 178 | struct gpu_ops *gops = &g->ops; |
179 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; | 179 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; |
180 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
180 | 181 | ||
181 | *gops = gm20b_ops; | 182 | *gops = gm20b_ops; |
182 | gops->securegpccs = false; | 183 | gops->securegpccs = false; |
183 | #ifdef CONFIG_TEGRA_ACR | 184 | #ifdef CONFIG_TEGRA_ACR |
184 | if (tegra_platform_is_linsim()) { | 185 | if (platform->is_fmodel) { |
185 | gops->privsecurity = 1; | 186 | gops->privsecurity = 1; |
186 | } else { | 187 | } else { |
187 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & | 188 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & |
@@ -193,7 +194,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
193 | } | 194 | } |
194 | } | 195 | } |
195 | #else | 196 | #else |
196 | if (tegra_platform_is_linsim()) { | 197 | if (platform->is_fmodel) { |
197 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 198 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
198 | gops->privsecurity = 0; | 199 | gops->privsecurity = 0; |
199 | } else { | 200 | } else { |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 56df6a5d..fee9a807 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -48,6 +48,7 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
48 | u32 compbit_backing_size; | 48 | u32 compbit_backing_size; |
49 | 49 | ||
50 | int err; | 50 | int err; |
51 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
51 | 52 | ||
52 | gk20a_dbg_fn(""); | 53 | gk20a_dbg_fn(""); |
53 | 54 | ||
@@ -80,7 +81,7 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
80 | gk20a_dbg_info("max comptag lines : %d", | 81 | gk20a_dbg_info("max comptag lines : %d", |
81 | max_comptag_lines); | 82 | max_comptag_lines); |
82 | 83 | ||
83 | if (tegra_platform_is_linsim()) | 84 | if (platform->is_fmodel) |
84 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | 85 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); |
85 | else | 86 | else |
86 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | 87 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); |