diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-21 00:56:39 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-29 16:29:46 -0400 |
commit | d1b0920b3f595b57a38f807b040634a331aa1ddd (patch) | |
tree | 1cfeca6d03cdb51afc97bace90786f3344807e6f | |
parent | 11009e0e69a497780ddb918fab89da62089510ce (diff) |
gpu: nvgpu: gv11b: multiple sm support
-Calculate sm reg offset by using gpc, tpc and sm numbers
-Init get_esr_sm_sel gr ops
JIRA GPUT19X-75
Change-Id: I74cfcae07e385cdad51774b963380c0633adfecf
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1506152
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 75 |
1 files changed, 56 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 59865a0f..e4826376 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -111,6 +111,15 @@ static bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) | |||
111 | return valid; | 111 | return valid; |
112 | } | 112 | } |
113 | 113 | ||
114 | static u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm) | ||
115 | { | ||
116 | |||
117 | u32 sm_pri_stride = nvgpu_get_litter_value(g, GPU_LIT_SM_PRI_STRIDE); | ||
118 | u32 sm_offset = sm_pri_stride * sm; | ||
119 | |||
120 | return sm_offset; | ||
121 | } | ||
122 | |||
114 | static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, | 123 | static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, |
115 | bool *post_event, struct channel_gk20a *fault_ch, | 124 | bool *post_event, struct channel_gk20a *fault_ch, |
116 | u32 *hww_global_esr) | 125 | u32 *hww_global_esr) |
@@ -580,7 +589,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
580 | } | 589 | } |
581 | 590 | ||
582 | static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | 591 | static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, |
583 | bool *post_event, struct channel_gk20a *fault_ch, | 592 | u32 sm, bool *post_event, struct channel_gk20a *fault_ch, |
584 | u32 *hww_global_esr) | 593 | u32 *hww_global_esr) |
585 | { | 594 | { |
586 | int ret = 0; | 595 | int ret = 0; |
@@ -1629,15 +1638,16 @@ static void gr_gv11b_get_access_map(struct gk20a *g, | |||
1629 | * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing | 1638 | * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing |
1630 | */ | 1639 | */ |
1631 | static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | 1640 | static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, |
1632 | u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, | 1641 | u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, |
1633 | bool sm_debugger_attached, struct channel_gk20a *fault_ch, | 1642 | bool sm_debugger_attached, struct channel_gk20a *fault_ch, |
1634 | bool *early_exit, bool *ignore_debugger) | 1643 | bool *early_exit, bool *ignore_debugger) |
1635 | { | 1644 | { |
1636 | int ret; | 1645 | int ret; |
1637 | bool cilp_enabled = false; | 1646 | bool cilp_enabled = false; |
1638 | u32 global_mask = 0, dbgr_control0, global_esr_copy; | 1647 | u32 global_mask = 0, dbgr_control0, global_esr_copy; |
1639 | u32 offset = proj_gpc_stride_v() * gpc + | 1648 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + |
1640 | proj_tpc_in_gpc_stride_v() * tpc; | 1649 | gk20a_gr_tpc_offset(g, tpc) + |
1650 | gv11b_gr_sm_offset(g, sm); | ||
1641 | 1651 | ||
1642 | *early_exit = false; | 1652 | *early_exit = false; |
1643 | *ignore_debugger = false; | 1653 | *ignore_debugger = false; |
@@ -1646,8 +1656,9 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1646 | cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == | 1656 | cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == |
1647 | NVGPU_COMPUTE_PREEMPTION_MODE_CILP); | 1657 | NVGPU_COMPUTE_PREEMPTION_MODE_CILP); |
1648 | 1658 | ||
1649 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n", | 1659 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1650 | gpc, tpc, global_esr); | 1660 | "SM Exception received on gpc %d tpc %d sm %d = 0x%08x", |
1661 | gpc, tpc, sm, global_esr); | ||
1651 | 1662 | ||
1652 | if (cilp_enabled && sm_debugger_attached) { | 1663 | if (cilp_enabled && sm_debugger_attached) { |
1653 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) | 1664 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) |
@@ -1665,20 +1676,23 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1665 | *ignore_debugger = true; | 1676 | *ignore_debugger = true; |
1666 | 1677 | ||
1667 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1678 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1668 | "CILP: starting wait for LOCKED_DOWN on gpc %d tpc %d\n", | 1679 | "CILP: starting wait for LOCKED_DOWN on " |
1669 | gpc, tpc); | 1680 | "gpc %d tpc %d sm %d", |
1681 | gpc, tpc, sm); | ||
1670 | 1682 | ||
1671 | if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) { | 1683 | if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) { |
1672 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1684 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1673 | "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", | 1685 | "CILP: Broadcasting STOP_TRIGGER from " |
1674 | gpc, tpc); | 1686 | "gpc %d tpc %d sm %d", |
1687 | gpc, tpc, sm); | ||
1675 | gk20a_suspend_all_sms(g, global_mask, false); | 1688 | gk20a_suspend_all_sms(g, global_mask, false); |
1676 | 1689 | ||
1677 | gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); | 1690 | gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); |
1678 | } else { | 1691 | } else { |
1679 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1692 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1680 | "CILP: STOP_TRIGGER from gpc %d tpc %d\n", | 1693 | "CILP: STOP_TRIGGER from " |
1681 | gpc, tpc); | 1694 | "gpc %d tpc %d sm %d", |
1695 | gpc, tpc, sm); | ||
1682 | gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); | 1696 | gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); |
1683 | } | 1697 | } |
1684 | 1698 | ||
@@ -1686,8 +1700,9 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1686 | global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); | 1700 | global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); |
1687 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); | 1701 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); |
1688 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1702 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1689 | "CILP: HWWs cleared for gpc %d tpc %d\n", | 1703 | "CILP: HWWs cleared for " |
1690 | gpc, tpc); | 1704 | "gpc %d tpc %d sm %d", |
1705 | gpc, tpc, sm); | ||
1691 | 1706 | ||
1692 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); | 1707 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); |
1693 | ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch); | 1708 | ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch); |
@@ -1699,8 +1714,9 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1699 | dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); | 1714 | dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); |
1700 | if (dbgr_control0 & gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f()) { | 1715 | if (dbgr_control0 & gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f()) { |
1701 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1716 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1702 | "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", | 1717 | "CILP: clearing SINGLE_STEP_MODE " |
1703 | gpc, tpc); | 1718 | "before resume for gpc %d tpc %d sm %d", |
1719 | gpc, tpc, sm); | ||
1704 | dbgr_control0 = set_field(dbgr_control0, | 1720 | dbgr_control0 = set_field(dbgr_control0, |
1705 | gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(), | 1721 | gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(), |
1706 | gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f()); | 1722 | gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f()); |
@@ -1708,12 +1724,14 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1708 | } | 1724 | } |
1709 | 1725 | ||
1710 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1726 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1711 | "CILP: resume for gpc %d tpc %d\n", | 1727 | "CILP: resume for gpc %d tpc %d sm %d", |
1712 | gpc, tpc); | 1728 | gpc, tpc, sm); |
1713 | gk20a_resume_single_sm(g, gpc, tpc); | 1729 | gk20a_resume_single_sm(g, gpc, tpc); |
1714 | 1730 | ||
1715 | *ignore_debugger = true; | 1731 | *ignore_debugger = true; |
1716 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); | 1732 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1733 | "CILP: All done on gpc %d, tpc %d sm %d", | ||
1734 | gpc, tpc, sm); | ||
1717 | } | 1735 | } |
1718 | 1736 | ||
1719 | *early_exit = true; | 1737 | *early_exit = true; |
@@ -2320,6 +2338,24 @@ static int gr_gv11b_init_fs_state(struct gk20a *g) | |||
2320 | return gr_gm20b_init_fs_state(g); | 2338 | return gr_gm20b_init_fs_state(g); |
2321 | } | 2339 | } |
2322 | 2340 | ||
2341 | static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | ||
2342 | u32 *esr_sm_sel) | ||
2343 | { | ||
2344 | u32 reg_val; | ||
2345 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | ||
2346 | |||
2347 | reg_val = gk20a_readl(g, gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r() + offset); | ||
2348 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2349 | "sm tpc esr sm sel reg val: 0x%x", reg_val); | ||
2350 | *esr_sm_sel = 0; | ||
2351 | if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(reg_val)) | ||
2352 | *esr_sm_sel = 1; | ||
2353 | if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(reg_val)) | ||
2354 | *esr_sm_sel |= 1 << 1; | ||
2355 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2356 | "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); | ||
2357 | } | ||
2358 | |||
2323 | void gv11b_init_gr(struct gpu_ops *gops) | 2359 | void gv11b_init_gr(struct gpu_ops *gops) |
2324 | { | 2360 | { |
2325 | gp10b_init_gr(gops); | 2361 | gp10b_init_gr(gops); |
@@ -2381,4 +2417,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2381 | gops->gr.set_czf_bypass = NULL; | 2417 | gops->gr.set_czf_bypass = NULL; |
2382 | gops->gr.handle_gpc_gpcmmu_exception = | 2418 | gops->gr.handle_gpc_gpcmmu_exception = |
2383 | gr_gv11b_handle_gpc_gpcmmu_exception; | 2419 | gr_gv11b_handle_gpc_gpcmmu_exception; |
2420 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; | ||
2384 | } | 2421 | } |