gpu: nvgpu: voltage changes

- added voltage interface & ctrl defines.

JIRA DNVGPU-122

Change-Id: Ia1a4c655c3c5faa638cafcdc75bdfb0e3c3be54f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1222775
(cherry picked from commit 46ff4d54d3cc02d9f039091f09eea09a5d6c22ce)
Reviewed-on: http://git-master/r/1244654
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 385 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
index 90a3bd89..04c7c4d1 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h
@@ -15,17 +15,94 @@
 #ifndef _ctrlvolt_h_
 #define _ctrlvolt_h_
 
-#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS                                 \
+#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS   \
         CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
 
 #include "ctrlperf.h"
 #include "ctrlboardobj.h"
 
-#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES                0x04
-#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES              (8)
-#define CTRL_VOLT_DOMAIN_INVALID                             0x00
-#define CTRL_VOLT_DOMAIN_LOGIC                               0x01
-#define CLK_PROG_VFE_ENTRY_LOGIC                             0x00
+#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES   0x04
+#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8)
+#define CTRL_VOLT_DOMAIN_INVALID        0x00
+#define CTRL_VOLT_DOMAIN_LOGIC          0x01
+#define CLK_PROG_VFE_ENTRY_LOGIC        0x00
+
+/*
+ * Macros for Voltage Domain HAL.
+ */
+#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00
+#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL  0x01
+
+/*
+ * Macros for Voltage Domains.
+ */
+#define CTRL_VOLT_DOMAIN_INVALID        0x00
+#define CTRL_VOLT_DOMAIN_LOGIC          0x01
+#define CTRL_VOLT_DOMAIN_SRAM           0x02
+
+/*!
+ * Special value corresponding to an invalid Voltage Rail Index.
+ */
+#define CTRL_VOLT_RAIL_INDEX_INVALID    \
+                        CTRL_BOARDOBJ_IDX_INVALID
+
+/*!
+ * Special value corresponding to an invalid Voltage Device Index.
+ */
+#define CTRL_VOLT_DEVICE_INDEX_INVALID  \
+                        CTRL_BOARDOBJ_IDX_INVALID
+
+/*!
+ * Special value corresponding to an invalid Voltage Policy Index.
+ */
+#define CTRL_VOLT_POLICY_INDEX_INVALID  \
+                        CTRL_BOARDOBJ_IDX_INVALID
+
+enum nv_pmu_pmgr_pwm_source {
+        NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
+        NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1 = 5,
+        NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
+        NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
+};
+
+/*!
+ * Macros for Voltage Device Types.
+ */
+#define CTRL_VOLT_DEVICE_TYPE_INVALID           0x00
+#define CTRL_VOLT_DEVICE_TYPE_PWM               0x03
+
+/*
+ * Macros for Volt Device Operation types.
+ */
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE       0x02
+#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE        0x03
+
+/*!
+ * Macros for Voltage Domains.
+ */
+#define CTRL_VOLT_DOMAIN_INVALID        0x00
+#define CTRL_VOLT_DOMAIN_LOGIC          0x01
+#define CTRL_VOLT_DOMAIN_SRAM           0x02
+
+/*!
+ * Macros for Volt Policy types.
+ *
+ * Virtual VOLT_POLICY types are indexed starting from 0xFF.
+ */
+#define CTRL_VOLT_POLICY_TYPE_INVALID           0x00
+#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL       0x01
+#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP     0x02
+#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP    0x03
+#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL        0xFE
+#define CTRL_VOLT_POLICY_TYPE_UNKNOWN           0xFF
+
+/*!
+ * Macros for Volt Policy Client types.
+ */
+#define CTRL_VOLT_POLICY_CLIENT_INVALID                 0x00
+#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ        0x01
 
 struct ctrl_volt_volt_rail_list_item {
         u8 rail_idx;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 2903cc9d..18f68558 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -27,6 +27,7 @@
 #include "pmuif/gpmuifclk.h"
 #include "pmuif/gpmuifperf.h"
 #include "pmuif/gpmuifpmgr.h"
+#include "pmuif/gpmuifvolt.h"
 
 /* defined by pmu hw spec */
 #define GK20A_PMU_VA_SIZE               (512 * 1024 * 1024)
@@ -181,6 +182,7 @@ struct pmu_ucode_desc_v1 {
 #define PMU_UNIT_FECS_MEM_OVERRIDE      (0x1E)
 #define PMU_UNIT_CLK             (0x0D)
 #define PMU_UNIT_PMGR            (0x18)
+#define PMU_UNIT_VOLT            (0x0E)
 
 #define PMU_UNIT_END            (0x23)
 
@@ -359,6 +361,7 @@ struct pmu_cmd {
                 struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram;
                 struct nv_pmu_boardobj_cmd boardobj;
                 struct nv_pmu_perf_cmd perf;
+                struct nv_pmu_volt_cmd volt;
                 struct nv_pmu_clk_cmd clk;
                 struct nv_pmu_pmgr_cmd pmgr;
         } cmd;
@@ -375,6 +378,7 @@ struct pmu_msg {
                 struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram;
                 struct nv_pmu_boardobj_msg boardobj;
                 struct nv_pmu_perf_msg perf;
+                struct nv_pmu_volt_msg volt;
                 struct nv_pmu_clk_msg clk;
                 struct nv_pmu_pmgr_msg pmgr;
         } msg;
@@ -812,5 +816,4 @@ int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct mem_desc *mem,
 int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem,
                 u32 size);
 
-void print_vbios_table(u8 *msg, u8 *buff, int size);
 #endif /*__PMU_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.h b/drivers/gpu/nvgpu/gm206/bios_gm206.h
index f8187631..53b82485 100644
--- a/drivers/gpu/nvgpu/gm206/bios_gm206.h
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.h
@@ -40,6 +40,9 @@ enum {
         POWER_SENSORS_TABLE = 0xA,
         POWER_CAPPING_TABLE = 0xB,
         POWER_TOPOLOGY_TABLE = 0xF,
+        VOLTAGE_RAIL_TABLE = 26,
+        VOLTAGE_DEVICE_TABLE,
+        VOLTAGE_POLICY_TABLE,
 };
 
 enum {
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h
index c480b1cf..28e27bb7 100644
--- a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h
+++ b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h
@@ -13,21 +13,307 @@
 #ifndef _GPMUIFVOLT_H_
 #define _GPMUIFVOLT_H_
 
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+#include "pmuif/gpmuifboardobj.h"
+#include "gk20a/pmu_common.h"
 #include "ctrl/ctrlvolt.h"
 
+#define NV_PMU_VOLT_VALUE_0V_IN_UV      (0)
+
+/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */
+
+#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL              0x00
+#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE    0x01
+#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY    0x02
+
+
+struct nv_pmu_volt_volt_rail_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_rail_boardobj_set {
+
+        struct nv_pmu_boardobj super;
+        u8 rel_limit_vfe_equ_idx;
+        u8 alt_rel_limit_vfe_equ_idx;
+        u8 ov_limit_vfe_equ_idx;
+        u8 vmin_limit_vfe_equ_idx;
+        u8 volt_margin_limit_vfe_equ_idx;
+        u8 pwr_equ_idx;
+        u8 volt_dev_idx_default;
+        struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
+        s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
+};
+
+union nv_pmu_volt_volt_rail_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_volt_volt_rail_boardobj_set super;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail);
+
+/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */
+
+struct nv_pmu_volt_volt_device_boardobjgrp_set_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_device_boardobj_set {
+        struct nv_pmu_boardobj super;
+        u32 switch_delay_us;
+        u32 voltage_min_uv;
+        u32 voltage_max_uv;
+        u32 volt_step_uv;
+};
+
+struct nv_pmu_volt_volt_device_vid_boardobj_set {
+        struct nv_pmu_volt_volt_device_boardobj_set super;
+        s32 voltage_base_uv;
+        s32 voltage_offset_scale_uv;
+        u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES];
+        u8 vsel_mask;
+};
+
+struct nv_pmu_volt_volt_device_pwm_boardobj_set {
+        struct nv_pmu_volt_volt_device_boardobj_set super;
+        u32 raw_period;
+        s32 voltage_base_uv;
+        s32 voltage_offset_scale_uv;
+        enum nv_pmu_pmgr_pwm_source pwm_source;
+};
+
+union nv_pmu_volt_volt_device_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_volt_volt_device_boardobj_set super;
+        struct nv_pmu_volt_volt_device_vid_boardobj_set vid;
+        struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device);
+
+/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */
+struct nv_pmu_volt_volt_policy_boardobjgrp_set_header {
+
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_policy_boardobj_set {
+        struct nv_pmu_boardobj super;
+};
+struct nv_pmu_volt_volt_policy_sr_boardobj_set {
+        struct nv_pmu_volt_volt_policy_boardobj_set super;
+        u8 rail_idx;
+};
+
+struct nv_pmu_volt_volt_policy_splt_r_boardobj_set {
+        struct nv_pmu_volt_volt_policy_boardobj_set super;
+        u8 rail_idx_master;
+        u8 rail_idx_slave;
+        u8 delta_min_vfe_equ_idx;
+        u8 delta_max_vfe_equ_idx;
+        s32 offset_delta_min_uv;
+        s32 offset_delta_max_uv;
+};
+
+struct nv_pmu_volt_volt_policy_srms_boardobj_set {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
+        u16 inter_switch_delayus;
+};
+
+/* sr - > single_rail */
+struct nv_pmu_volt_volt_policy_srss_boardobj_set {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super;
+};
+
+union nv_pmu_volt_volt_policy_boardobj_set_union {
+        struct nv_pmu_boardobj board_obj;
+        struct nv_pmu_volt_volt_policy_boardobj_set super;
+        struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail;
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail;
+        struct nv_pmu_volt_volt_policy_srms_boardobj_set
+                        split_rail_m_s;
+        struct nv_pmu_volt_volt_policy_srss_boardobj_set
+                        split_rail_s_s;
+};
+
+NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy);
+
+/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */
+struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_rail_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+        u32 curr_volt_defaultu_v;
+        u32 rel_limitu_v;
+        u32 alt_rel_limitu_v;
+        u32 ov_limitu_v;
+        u32 max_limitu_v;
+        u32 vmin_limitu_v;
+        s32 volt_margin_limitu_v;
+        u32 rsvd;
+};
+
+union nv_pmu_volt_volt_rail_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_volt_volt_rail_boardobj_get_status super;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail);
+
+/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */
+struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_device_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+};
+
+union nv_pmu_volt_volt_device_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_volt_volt_device_boardobj_get_status super;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device);
+
+/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */
+struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header {
+        struct nv_pmu_boardobjgrp_e32 super;
+};
+
+struct nv_pmu_volt_volt_policy_boardobj_get_status {
+        struct nv_pmu_boardobj_query super;
+        u32 offset_volt_requ_v;
+        u32 offset_volt_curru_v;
+};
+
+struct nv_pmu_volt_volt_policy_sr_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_boardobj_get_status super;
+        u32 curr_voltu_v;
+};
+
+struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_boardobj_get_status super;
+        s32 delta_minu_v;
+        s32 delta_maxu_v;
+        s32 orig_delta_minu_v;
+        s32 orig_delta_maxu_v;
+        u32 curr_volt_masteru_v;
+        u32 curr_volt_slaveu_v;
+        bool b_violation;
+};
+
+/* srms -> split_rail_multi_step */
+struct nv_pmu_volt_volt_policy_srms_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
+};
+
+/* srss -> split_rail_single_step */
+struct nv_pmu_volt_volt_policy_srss_boardobj_get_status {
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super;
+};
+
+union nv_pmu_volt_volt_policy_boardobj_get_status_union {
+        struct nv_pmu_boardobj_query board_obj;
+        struct nv_pmu_volt_volt_policy_boardobj_get_status super;
+        struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail;
+        struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail;
+        struct nv_pmu_volt_volt_policy_srms_boardobj_get_status
+                        split_rail_m_s;
+        struct nv_pmu_volt_volt_policy_srss_boardobj_get_status
+                        split_rail_s_s;
+};
+
+NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy);
+
+struct nv_pmu_volt_policy_voltage_data {
+        u8 policy_idx;
+        struct ctrl_perf_volt_rail_list
+        rail_list;
+};
+
+struct nv_pmu_volt_rail_get_voltage {
+        u8 rail_idx;
+        u32 voltage_uv;
+};
+
+#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET     (0x00000000)
+#define NV_PMU_VOLT_CMD_ID_RPC                          (0x00000001)
+#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS      (0x00000002)
+
 /*!
-* Structure containing the number of voltage rails and the list of rail items
-* @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM.
+* PMU VOLT RPC calls.
 */
+#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000)
+#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE      (0x00000002)
+#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE        (0x00000003)
+
+struct nv_pmu_volt_cmd_rpc {
+        u8 cmd_type;
+        u8 pad[3];
+        struct nv_pmu_allocation request;
+};
+
+#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET        \
+        offsetof(struct nv_pmu_volt_cmd_rpc, request)
+
+struct nv_pmu_volt_cmd {
+        union {
+                u8 cmd_type;
+                struct nv_pmu_boardobj_cmd_grp grp_set;
+                struct nv_pmu_volt_cmd_rpc rpc;
+                struct nv_pmu_boardobj_cmd_grp grp_get_status;
+        };
+};
+
+struct nv_pmu_volt_rpc {
+        u8 function;
+        bool b_supported;
+        bool b_success;
+        flcn_status flcn_status;
+        union {
+                struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data;
+                struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage;
+        } params;
+};
+
+/*!
+* VOLT MSG ID definitions
+*/
+#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET     (0x00000000)
+#define NV_PMU_VOLT_MSG_ID_RPC                          (0x00000001)
+#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS      (0x00000002)
+
+/*!
+* Message carrying the result of the VOLT RPC execution.
+*/
+struct nv_pmu_volt_msg_rpc {
+        u8 msg_type;
+        u8 rsvd[3];
+        struct nv_pmu_allocation response;
+};
+
+#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET        \
+                offsetof(struct nv_pmu_volt_msg_rpc, response)
+
+struct nv_pmu_volt_msg {
+        union {
+                u8 msg_type;
+                struct nv_pmu_boardobj_msg_grp grp_set;
+                struct nv_pmu_volt_msg_rpc rpc;
+                struct nv_pmu_boardobj_msg_grp grp_get_status;
+        };
+};
+
+#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS         (2)
+
 struct nv_pmu_volt_volt_rail_list {
-        /*!
-        * Number of VOLT_RAILs that require the voltage change.
-        */
         u8 num_rails;
-        /*!
-        * List of @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM entries.
-        */
-        struct ctrl_perf_volt_rail_list_item rails[2];
+        struct ctrl_perf_volt_rail_list_item
+        rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS];
 };
 
 #endif  /* _GPMUIFVOLT_H_*/