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authorLakshmanan M <lm@nvidia.com>2016-07-28 07:23:31 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:18 -0500
commitcae5d380d8b465f4d1389ae80d6cec1458951e29 (patch)
tree702e29a4ea43698a0ca4007565bb06051052ec5f
parent436109f46d49a24b69bab7c85b112f192ab002c0 (diff)
gpu: nvgpu: Add preemption mode support for gp10x
Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x family gr class (PASCAL_B and PASCAL_COMPUTE_B). Bug 200221149 Change-Id: Ia8b781c5baedba660db5997f190a0b363286ed7f Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1193209 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.c118
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c24
2 files changed, 136 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
index 9d6ce6ec..01d06975 100644
--- a/drivers/gpu/nvgpu/gp106/gr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -102,6 +102,123 @@ static void gr_gp106_cb_size_default(struct gk20a *g)
102 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 102 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
103} 103}
104 104
105static int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
106 struct gr_ctx_desc *gr_ctx,
107 struct vm_gk20a *vm, u32 class,
108 u32 graphics_preempt_mode,
109 u32 compute_preempt_mode)
110{
111 int err = 0;
112
113 if (class == PASCAL_B && g->gr.t18x.ctx_vars.force_preemption_gfxp)
114 graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP;
115
116 if (class == PASCAL_COMPUTE_B &&
117 g->gr.t18x.ctx_vars.force_preemption_cilp)
118 compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
119
120 /* check for invalid combinations */
121 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
122 return -EINVAL;
123
124 if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) &&
125 (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP))
126 return -EINVAL;
127
128 /* set preemption modes */
129 switch (graphics_preempt_mode) {
130 case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP:
131 {
132 u32 spill_size =
133 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
134 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
135 u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
136 gr_scc_pagepool_total_pages_byte_granularity_v();
137 u32 betacb_size = g->gr.attrib_cb_default_size +
138 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
139 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
140 u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
141 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
142 g->gr.max_tpc_count;
143 attrib_cb_size = ALIGN(attrib_cb_size, 128);
144
145 gk20a_dbg_info("gfxp context spill_size=%d", spill_size);
146 gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size);
147 gk20a_dbg_info("gfxp context attrib_cb_size=%d",
148 attrib_cb_size);
149
150 err = gr_gp10b_alloc_buffer(vm,
151 g->gr.t18x.ctx_vars.preempt_image_size,
152 &gr_ctx->t18x.preempt_ctxsw_buffer);
153 if (err) {
154 gk20a_err(dev_from_gk20a(g),
155 "cannot allocate preempt buffer");
156 goto fail;
157 }
158
159 err = gr_gp10b_alloc_buffer(vm,
160 spill_size,
161 &gr_ctx->t18x.spill_ctxsw_buffer);
162 if (err) {
163 gk20a_err(dev_from_gk20a(g),
164 "cannot allocate spill buffer");
165 goto fail_free_preempt;
166 }
167
168 err = gr_gp10b_alloc_buffer(vm,
169 attrib_cb_size,
170 &gr_ctx->t18x.betacb_ctxsw_buffer);
171 if (err) {
172 gk20a_err(dev_from_gk20a(g),
173 "cannot allocate beta buffer");
174 goto fail_free_spill;
175 }
176
177 err = gr_gp10b_alloc_buffer(vm,
178 pagepool_size,
179 &gr_ctx->t18x.pagepool_ctxsw_buffer);
180 if (err) {
181 gk20a_err(dev_from_gk20a(g),
182 "cannot allocate page pool");
183 goto fail_free_betacb;
184 }
185
186 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
187 break;
188 }
189
190 case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI:
191 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
192 break;
193
194 default:
195 break;
196 }
197
198 if (class == PASCAL_COMPUTE_B) {
199 switch (compute_preempt_mode) {
200 case NVGPU_COMPUTE_PREEMPTION_MODE_WFI:
201 case NVGPU_COMPUTE_PREEMPTION_MODE_CTA:
202 case NVGPU_COMPUTE_PREEMPTION_MODE_CILP:
203 gr_ctx->compute_preempt_mode = compute_preempt_mode;
204 break;
205 default:
206 break;
207 }
208 }
209
210 return 0;
211
212fail_free_betacb:
213 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
214fail_free_spill:
215 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
216fail_free_preempt:
217 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
218fail:
219 return err;
220}
221
105void gp106_init_gr(struct gpu_ops *gops) 222void gp106_init_gr(struct gpu_ops *gops)
106{ 223{
107 gp10b_init_gr(gops); 224 gp10b_init_gr(gops);
@@ -110,4 +227,5 @@ void gp106_init_gr(struct gpu_ops *gops)
110 gops->gr.handle_sw_method = gr_gp106_handle_sw_method; 227 gops->gr.handle_sw_method = gr_gp106_handle_sw_method;
111 gops->gr.cb_size_default = gr_gp106_cb_size_default; 228 gops->gr.cb_size_default = gr_gp106_cb_size_default;
112 gops->gr.init_preemption_state = NULL; 229 gops->gr.init_preemption_state = NULL;
230 gops->gr.set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode;
113} 231}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 374242bf..ee73fed1 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -992,9 +992,15 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
992 compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; 992 compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP;
993 993
994 if (graphics_preempt_mode || compute_preempt_mode) { 994 if (graphics_preempt_mode || compute_preempt_mode) {
995 err = gr_gp10b_set_ctxsw_preemption_mode(g, *gr_ctx, vm, 995 if (g->ops.gr.set_ctxsw_preemption_mode) {
996 err = g->ops.gr.set_ctxsw_preemption_mode(g, *gr_ctx, vm,
996 class, graphics_preempt_mode, compute_preempt_mode); 997 class, graphics_preempt_mode, compute_preempt_mode);
997 if (err) 998 if (err) {
999 gk20a_err(dev_from_gk20a(g),
1000 "set_ctxsw_preemption_mode failed");
1001 goto fail_free_gk20a_ctx;
1002 }
1003 } else
998 goto fail_free_gk20a_ctx; 1004 goto fail_free_gk20a_ctx;
999 } 1005 }
1000 1006
@@ -2067,10 +2073,15 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
2067 vm = ch->vm; 2073 vm = ch->vm;
2068 } 2074 }
2069 2075
2070 err = gr_gp10b_set_ctxsw_preemption_mode(g, gr_ctx, vm, class, 2076 if (g->ops.gr.set_ctxsw_preemption_mode) {
2071 graphics_preempt_mode, compute_preempt_mode); 2077 err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class,
2072 if (err) 2078 graphics_preempt_mode, compute_preempt_mode);
2073 return err; 2079 if (err) {
2080 gk20a_err(dev_from_gk20a(g),
2081 "set_ctxsw_preemption_mode failed");
2082 return err;
2083 }
2084 }
2074 2085
2075 if (gk20a_mem_begin(g, mem)) 2086 if (gk20a_mem_begin(g, mem))
2076 return -ENOMEM; 2087 return -ENOMEM;
@@ -2225,6 +2236,7 @@ void gp10b_init_gr(struct gpu_ops *gops)
2225 gops->gr.get_lrf_tex_ltc_dram_override = get_ecc_override_val; 2236 gops->gr.get_lrf_tex_ltc_dram_override = get_ecc_override_val;
2226 gops->gr.suspend_contexts = gr_gp10b_suspend_contexts; 2237 gops->gr.suspend_contexts = gr_gp10b_suspend_contexts;
2227 gops->gr.set_preemption_mode = gr_gp10b_set_preemption_mode; 2238 gops->gr.set_preemption_mode = gr_gp10b_set_preemption_mode;
2239 gops->gr.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode;
2228 gops->gr.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags; 2240 gops->gr.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags;
2229 gops->gr.fuse_override = gp10b_gr_fuse_override; 2241 gops->gr.fuse_override = gp10b_gr_fuse_override;
2230 gops->gr.load_smid_config = gr_gp10b_load_smid_config; 2242 gops->gr.load_smid_config = gr_gp10b_load_smid_config;