gpu: nvgpu: Implement dGPU simulation support

Implement support for dGPU fmodel. The message protocol is slightly
different and accessed via BAR0 aperture.

JIRA NVGPUT-41

Change-Id: Ide3c52a751530f520854965c1eba19fa8339a315
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694963
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 2582 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index c51a0948..31483c5d 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -48,6 +48,7 @@ nvgpu-y := \
         common/linux/channel.o \
         common/linux/ce2.o \
         common/linux/sim.o \
+        common/linux/sim_pci.o \
         common/linux/os_sched.o \
         common/linux/nvlink.o \
         common/mm/nvgpu_allocator.o \
diff --git a/drivers/gpu/nvgpu/common/linux/hw_sim_pci.h b/drivers/gpu/nvgpu/common/linux/hw_sim_pci.h
new file mode 100644
index 00000000..32dbeb4b
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/hw_sim_pci.h
@@ -0,0 +1,2169 @@
+/*
+ * Copyright (c) 2012-2018, NVIDIA Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+ /*
+  * Function naming determines intended use:
+  *
+  *     <x>_r(void) : Returns the offset for register <x>.
+  *
+  *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+  *
+  *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+  *
+  *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+  *         and masked to place it at field <y> of register <x>.  This value
+  *         can be |'d with others to produce a full register value for
+  *         register <x>.
+  *
+  *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+  *         value can be ~'d and then &'d to clear the value of field <y> for
+  *         register <x>.
+  *
+  *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+  *         to place it at field <y> of register <x>.  This value can be |'d
+  *         with others to produce a full register value for <x>.
+  *
+  *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+  *         <x> value 'r' after being shifted to place its LSB at bit 0.
+  *         This value is suitable for direct comparison with other unshifted
+  *         values appropriate for use in field <y> of register <x>.
+  *
+  *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+  *         field <y> of register <x>.  This value is suitable for direct
+  *         comparison with unshifted values appropriate for use in field <y>
+  *         of register <x>.
+  */
+
+#ifndef __hw_sim_pci_h__
+#define __hw_sim_pci_h__
+/*This file is autogenerated.  Do not edit. */
+
+static inline u32 sim_r(void)
+{
+        return 0x0008f000U;
+}
+static inline u32 sim_send_ring_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_target_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_send_ring_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 sim_send_ring_target_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 sim_send_ring_target_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 sim_send_ring_target_phys_init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_send_ring_target_phys_init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_send_ring_target_phys__init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_send_ring_target_phys__init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_send_ring_target_phys__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_send_ring_target_phys__prod_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_send_ring_target_phys_nvm_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_send_ring_target_phys_nvm_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_send_ring_target_phys_pci_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_send_ring_target_phys_pci_f(void)
+{
+        return 0x2U;
+}
+static inline u32 sim_send_ring_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_send_ring_target_phys_pci_coherent_f(void)
+{
+        return 0x3U;
+}
+static inline u32 sim_send_ring_status_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_send_ring_status_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 sim_send_ring_status_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 sim_send_ring_status_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 sim_send_ring_status_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_status_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_status__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_status__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_status__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_status__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_status_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_send_ring_status_valid_f(void)
+{
+        return 0x8U;
+}
+static inline u32 sim_send_ring_size_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_send_ring_size_f(u32 v)
+{
+        return (v & 0x3U) << 4U;
+}
+static inline u32 sim_send_ring_size_m(void)
+{
+        return 0x3U << 4U;
+}
+static inline u32 sim_send_ring_size_v(u32 r)
+{
+        return (r >> 4U) & 0x3U;
+}
+static inline u32 sim_send_ring_size_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_size_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_size__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_size__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_size__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_size__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_size_4kb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_size_4kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_size_8kb_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_send_ring_size_8kb_f(void)
+{
+        return 0x10U;
+}
+static inline u32 sim_send_ring_size_12kb_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_send_ring_size_12kb_f(void)
+{
+        return 0x20U;
+}
+static inline u32 sim_send_ring_size_16kb_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_send_ring_size_16kb_f(void)
+{
+        return 0x30U;
+}
+static inline u32 sim_send_ring_gp_in_ring_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_send_ring_gp_in_ring_f(u32 v)
+{
+        return (v & 0x1) << 11U;
+}
+static inline u32 sim_send_ring_gp_in_ring_m(void)
+{
+        return 0x1 << 11U;
+}
+static inline u32 sim_send_ring_gp_in_ring_v(u32 r)
+{
+        return (r >> 11) & 0x1U;
+}
+static inline u32 sim_send_ring_gp_in_ring__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_gp_in_ring__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_gp_in_ring__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_gp_in_ring__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_gp_in_ring_no_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_gp_in_ring_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_gp_in_ring_yes_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_send_ring_gp_in_ring_yes_f(void)
+{
+        return 0x800U;
+}
+static inline u32 sim_send_ring_addr_lo_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_send_ring_addr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 sim_send_ring_addr_lo_m(void)
+{
+        return 0xfffffU << 12U;
+}
+static inline u32 sim_send_ring_addr_lo_v(u32 r)
+{
+        return (r >> 12U) & 0xfffffU;
+}
+static inline u32 sim_send_ring_addr_lo__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_addr_lo__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_addr_lo__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_addr_lo__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_hi_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 sim_send_ring_hi_addr_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_send_ring_hi_addr_f(u32 v)
+{
+        return (v & 0xfffffU) << 0U;
+}
+static inline u32 sim_send_ring_hi_addr_m(void)
+{
+        return 0xfffffU << 0U;
+}
+static inline u32 sim_send_ring_hi_addr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 sim_send_ring_hi_addr__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_hi_addr__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_ring_hi_addr__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_send_ring_hi_addr__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_send_put_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 sim_send_put_pointer_s(void)
+{
+        return 29U;
+}
+static inline u32 sim_send_put_pointer_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 3U;
+}
+static inline u32 sim_send_put_pointer_m(void)
+{
+        return 0x1fffffffU << 3U;
+}
+static inline u32 sim_send_put_pointer_v(u32 r)
+{
+        return (r >> 3U) & 0x1fffffffU;
+}
+static inline u32 sim_send_get_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 sim_send_get_pointer_s(void)
+{
+        return 29U;
+}
+static inline u32 sim_send_get_pointer_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 3U;
+}
+static inline u32 sim_send_get_pointer_m(void)
+{
+        return 0x1fffffffU << 3U;
+}
+static inline u32 sim_send_get_pointer_v(u32 r)
+{
+        return (r >> 3U) & 0x1fffffffU;
+}
+static inline u32 sim_recv_ring_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 sim_recv_ring_target_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_recv_ring_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 sim_recv_ring_target_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 sim_recv_ring_target_v(u32 r)
+{
+        return (r >> 0) & 0x3U;
+}
+static inline u32 sim_recv_ring_target_phys_init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_recv_ring_target_phys_init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_recv_ring_target_phys__init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_recv_ring_target_phys__init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_recv_ring_target_phys__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_recv_ring_target_phys__prod_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_recv_ring_target_phys_nvm_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_recv_ring_target_phys_nvm_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_recv_ring_target_phys_pci_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_recv_ring_target_phys_pci_f(void)
+{
+        return 0x2U;
+}
+static inline u32 sim_recv_ring_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_recv_ring_target_phys_pci_coherent_f(void)
+{
+        return 0x3U;
+}
+static inline u32 sim_recv_ring_status_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_recv_ring_status_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 sim_recv_ring_status_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 sim_recv_ring_status_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 sim_recv_ring_status_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_status_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_status__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_status__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_status__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_status__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_status_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_recv_ring_status_valid_f(void)
+{
+        return 0x8U;
+}
+static inline u32 sim_recv_ring_size_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_recv_ring_size_f(u32 v)
+{
+        return (v & 0x3U) << 4U;
+}
+static inline u32 sim_recv_ring_size_m(void)
+{
+        return 0x3U << 4U;
+}
+static inline u32 sim_recv_ring_size_v(u32 r)
+{
+        return (r >> 4U) & 0x3U;
+}
+static inline u32 sim_recv_ring_size_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_size_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_size__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_size__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_size__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_size__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_size_4kb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_size_4kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_size_8kb_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_recv_ring_size_8kb_f(void)
+{
+        return 0x10U;
+}
+static inline u32 sim_recv_ring_size_12kb_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_recv_ring_size_12kb_f(void)
+{
+        return 0x20U;
+}
+static inline u32 sim_recv_ring_size_16kb_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_recv_ring_size_16kb_f(void)
+{
+        return 0x30U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_v(u32 r)
+{
+        return (r >> 11U) & 0x1U;
+}
+static inline u32 sim_recv_ring_gp_in_ring__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_gp_in_ring__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_gp_in_ring__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_gp_in_ring__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_no_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_yes_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_recv_ring_gp_in_ring_yes_f(void)
+{
+        return 0x800U;
+}
+static inline u32 sim_recv_ring_addr_lo_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_recv_ring_addr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 sim_recv_ring_addr_lo_m(void)
+{
+        return 0xfffffU << 12U;
+}
+static inline u32 sim_recv_ring_addr_lo_v(u32 r)
+{
+        return (r >> 12U) & 0xfffffU;
+}
+static inline u32 sim_recv_ring_addr_lo__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_addr_lo__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_addr_lo__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_addr_lo__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_hi_r(void)
+{
+        return 0x00000014U;
+}
+static inline u32 sim_recv_ring_hi_addr_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_recv_ring_hi_addr_f(u32 v)
+{
+        return (v & 0xfffffU) << 0U;
+}
+static inline u32 sim_recv_ring_hi_addr_m(void)
+{
+        return 0xfffffU << 0U;
+}
+static inline u32 sim_recv_ring_hi_addr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 sim_recv_ring_hi_addr__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_hi_addr__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_ring_hi_addr__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_recv_ring_hi_addr__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_recv_put_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 sim_recv_put_pointer_s(void)
+{
+        return 11U;
+}
+static inline u32 sim_recv_put_pointer_f(u32 v)
+{
+        return (v & 0x7ffU) << 3U;
+}
+static inline u32 sim_recv_put_pointer_m(void)
+{
+        return 0x7ffU << 3U;
+}
+static inline u32 sim_recv_put_pointer_v(u32 r)
+{
+        return (r >> 3U) & 0x7ffU;
+}
+static inline u32 sim_recv_get_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 sim_recv_get_pointer_s(void)
+{
+        return 11U;
+}
+static inline u32 sim_recv_get_pointer_f(u32 v)
+{
+        return (v & 0x7ffU) << 3U;
+}
+static inline u32 sim_recv_get_pointer_m(void)
+{
+        return 0x7ffU << 3U;
+}
+static inline u32 sim_recv_get_pointer_v(u32 r)
+{
+        return (r >> 3U) & 0x7ffU;
+}
+static inline u32 sim_config_r(void)
+{
+        return 0x00000020U;
+}
+static inline u32 sim_config_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_config_mode_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 sim_config_mode_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 sim_config_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 sim_config_mode_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_config_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_config_mode_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_config_mode_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_config_channels_s(void)
+{
+        return 7U;
+}
+static inline u32 sim_config_channels_f(u32 v)
+{
+        return (v & 0x7fU) << 1U;
+}
+static inline u32 sim_config_channels_m(void)
+{
+        return 0x7fU << 1U;
+}
+static inline u32 sim_config_channels_v(u32 r)
+{
+        return (r >> 1U) & 0x7fU;
+}
+static inline u32 sim_config_channels_none_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_config_channels_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_config_cached_only_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_config_cached_only_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 sim_config_cached_only_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 sim_config_cached_only_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 sim_config_cached_only_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_config_cached_only_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_config_cached_only_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_config_cached_only_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 sim_config_validity_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_config_validity_f(u32 v)
+{
+        return (v & 0x3U) << 9U;
+}
+static inline u32 sim_config_validity_m(void)
+{
+        return 0x3U << 9U;
+}
+static inline u32 sim_config_validity_v(u32 r)
+{
+        return (r >> 9U) & 0x3U;
+}
+static inline u32 sim_config_validity__init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_config_validity__init_f(void)
+{
+        return 0x200U;
+}
+static inline u32 sim_config_validity_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_config_validity_valid_f(void)
+{
+        return 0x200U;
+}
+static inline u32 sim_config_simulation_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_config_simulation_f(u32 v)
+{
+        return (v & 0x3U) << 12U;
+}
+static inline u32 sim_config_simulation_m(void)
+{
+        return 0x3U << 12U;
+}
+static inline u32 sim_config_simulation_v(u32 r)
+{
+        return (r >> 12U) & 0x3U;
+}
+static inline u32 sim_config_simulation_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_config_simulation_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_config_simulation_fmodel_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_config_simulation_fmodel_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 sim_config_simulation_rtlsim_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_config_simulation_rtlsim_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 sim_config_secondary_display_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_config_secondary_display_f(u32 v)
+{
+        return (v & 0x1U) << 14U;
+}
+static inline u32 sim_config_secondary_display_m(void)
+{
+        return 0x1U << 14U;
+}
+static inline u32 sim_config_secondary_display_v(u32 r)
+{
+        return (r >> 14U) & 0x1U;
+}
+static inline u32 sim_config_secondary_display_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_config_secondary_display_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_config_secondary_display_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_config_secondary_display_enabled_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 sim_config_num_heads_s(void)
+{
+        return 8U;
+}
+static inline u32 sim_config_num_heads_f(u32 v)
+{
+        return (v & 0xffU) << 17U;
+}
+static inline u32 sim_config_num_heads_m(void)
+{
+        return 0xffU << 17U;
+}
+static inline u32 sim_config_num_heads_v(u32 r)
+{
+        return (r >> 17U) & 0xffU;
+}
+static inline u32 sim_event_ring_r(void)
+{
+        return 0x00000030U;
+}
+static inline u32 sim_event_ring_target_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_event_ring_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 sim_event_ring_target_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 sim_event_ring_target_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 sim_event_ring_target_phys_init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_event_ring_target_phys_init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_event_ring_target_phys__init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_event_ring_target_phys__init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_event_ring_target_phys__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_event_ring_target_phys__prod_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_event_ring_target_phys_nvm_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_event_ring_target_phys_nvm_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_event_ring_target_phys_pci_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_event_ring_target_phys_pci_f(void)
+{
+        return 0x2U;
+}
+static inline u32 sim_event_ring_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_event_ring_target_phys_pci_coherent_f(void)
+{
+        return 0x3U;
+}
+static inline u32 sim_event_ring_status_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_event_ring_status_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 sim_event_ring_status_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 sim_event_ring_status_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 sim_event_ring_status_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_status_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_status__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_status__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_status__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_status__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_status_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_event_ring_status_valid_f(void)
+{
+        return 0x8U;
+}
+static inline u32 sim_event_ring_size_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_event_ring_size_f(u32 v)
+{
+        return (v & 0x3U) << 4U;
+}
+static inline u32 sim_event_ring_size_m(void)
+{
+        return 0x3U << 4U;
+}
+static inline u32 sim_event_ring_size_v(u32 r)
+{
+        return (r >> 4U) & 0x3U;
+}
+static inline u32 sim_event_ring_size_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_size_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_size__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_size__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_size__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_size__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_size_4kb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_size_4kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_size_8kb_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_event_ring_size_8kb_f(void)
+{
+        return 0x10U;
+}
+static inline u32 sim_event_ring_size_12kb_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_event_ring_size_12kb_f(void)
+{
+        return 0x20U;
+}
+static inline u32 sim_event_ring_size_16kb_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_event_ring_size_16kb_f(void)
+{
+        return 0x30U;
+}
+static inline u32 sim_event_ring_gp_in_ring_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_event_ring_gp_in_ring_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 sim_event_ring_gp_in_ring_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 sim_event_ring_gp_in_ring_v(u32 r)
+{
+        return (r >> 11U) & 0x1U;
+}
+static inline u32 sim_event_ring_gp_in_ring__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_gp_in_ring__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_gp_in_ring__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_gp_in_ring__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_gp_in_ring_no_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_gp_in_ring_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_gp_in_ring_yes_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_event_ring_gp_in_ring_yes_f(void)
+{
+        return 0x800U;
+}
+static inline u32 sim_event_ring_addr_lo_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_event_ring_addr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 sim_event_ring_addr_lo_m(void)
+{
+        return 0xfffffU << 12U;
+}
+static inline u32 sim_event_ring_addr_lo_v(u32 r)
+{
+        return (r >> 12U) & 0xfffffU;
+}
+static inline u32 sim_event_ring_addr_lo__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_addr_lo__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_addr_lo__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_addr_lo__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_hi_v(void)
+{
+        return 0x00000034U;
+}
+static inline u32 sim_event_ring_hi_addr_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_event_ring_hi_addr_f(u32 v)
+{
+        return (v & 0xfffffU) << 0U;
+}
+static inline u32 sim_event_ring_hi_addr_m(void)
+{
+        return 0xfffffU << 0U;
+}
+static inline u32 sim_event_ring_hi_addr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 sim_event_ring_hi_addr__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_hi_addr__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_ring_hi_addr__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_event_ring_hi_addr__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_event_put_r(void)
+{
+        return 0x00000038U;
+}
+static inline u32 sim_event_put_pointer_s(void)
+{
+        return 30U;
+}
+static inline u32 sim_event_put_pointer_f(u32 v)
+{
+        return (v & 0x3fffffffU) << 2U;
+}
+static inline u32 sim_event_put_pointer_m(void)
+{
+        return 0x3fffffffU << 2U;
+}
+static inline u32 sim_event_put_pointer_v(u32 r)
+{
+        return (r >> 2U) & 0x3fffffffU;
+}
+static inline u32 sim_event_get_r(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 sim_event_get_pointer_s(void)
+{
+        return 30U;
+}
+static inline u32 sim_event_get_pointer_f(u32 v)
+{
+        return (v & 0x3fffffffU) << 2U;
+}
+static inline u32 sim_event_get_pointer_m(void)
+{
+        return 0x3fffffffU << 2U;
+}
+static inline u32 sim_event_get_pointer_v(u32 r)
+{
+        return (r >> 2U) & 0x3fffffffU;
+}
+static inline u32 sim_status_r(void)
+{
+        return 0x00000028U;
+}
+static inline u32 sim_status_send_put_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_status_send_put_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 sim_status_send_put_m(void)
+{
+        return 0x1 << 0U;
+}
+static inline u32 sim_status_send_put_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 sim_status_send_put__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_send_put__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_send_put_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_send_put_idle_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_send_put_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_send_put_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_status_send_get_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_status_send_get_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 sim_status_send_get_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 sim_status_send_get_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 sim_status_send_get__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_send_get__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_send_get_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_send_get_idle_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_send_get_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_send_get_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 sim_status_send_get_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_send_get_clear_f(void)
+{
+        return 0x2U;
+}
+static inline u32 sim_status_recv_put_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_status_recv_put_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 sim_status_recv_put_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 sim_status_recv_put_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 sim_status_recv_put__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_recv_put__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_recv_put_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_recv_put_idle_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_recv_put_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_recv_put_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 sim_status_recv_put_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_recv_put_clear_f(void)
+{
+        return 0x4U;
+}
+static inline u32 sim_status_recv_get_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_status_recv_get_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 sim_status_recv_get_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 sim_status_recv_get_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 sim_status_recv_get__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_recv_get__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_recv_get_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_recv_get_idle_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_recv_get_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_recv_get_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 sim_status_event_put_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_status_event_put_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 sim_status_event_put_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 sim_status_event_put_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 sim_status_event_put__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_event_put__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_event_put_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_event_put_idle_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_event_put_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_event_put_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 sim_status_event_put_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_event_put_clear_f(void)
+{
+        return 0x10U;
+}
+static inline u32 sim_status_event_get_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_status_event_get_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 sim_status_event_get_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 sim_status_event_get_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 sim_status_event_get__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_event_get__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_event_get_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_status_event_get_idle_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_status_event_get_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_status_event_get_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 sim_control_r(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 sim_control_send_put_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_control_send_put_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 sim_control_send_put_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 sim_control_send_put_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 sim_control_send_put__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_send_put__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_send_put_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_send_put_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_send_put_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_control_send_put_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_control_send_get_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_control_send_get_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 sim_control_send_get_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 sim_control_send_get_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 sim_control_send_get__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_send_get__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_send_get_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_send_get_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_send_get_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_control_send_get_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 sim_control_recv_put_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_control_recv_put_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 sim_control_recv_put_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 sim_control_recv_put_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 sim_control_recv_put__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_recv_put__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_recv_put_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_recv_put_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_recv_put_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_control_recv_put_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 sim_control_recv_get_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_control_recv_get_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 sim_control_recv_get_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 sim_control_recv_get_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 sim_control_recv_get__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_recv_get__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_recv_get_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_recv_get_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_recv_get_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_control_recv_get_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 sim_control_event_put_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_control_event_put_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 sim_control_event_put_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 sim_control_event_put_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 sim_control_event_put__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_event_put__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_event_put_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_event_put_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_event_put_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_control_event_put_enabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 sim_control_event_get_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_control_event_get_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 sim_control_event_get_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 sim_control_event_get_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 sim_control_event_get__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_event_get__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_event_get_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_control_event_get_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_control_event_get_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_control_event_get_enabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 sim_dma_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_target_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_dma_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 sim_dma_target_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 sim_dma_target_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 sim_dma_target_phys_init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_dma_target_phys_init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_dma_target_phys__init_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_dma_target_phys__init_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_dma_target_phys__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_dma_target_phys__prod_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_dma_target_phys_nvm_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_dma_target_phys_nvm_f(void)
+{
+        return 0x1U;
+}
+static inline u32 sim_dma_target_phys_pci_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_dma_target_phys_pci_f(void)
+{
+        return 0x2U;
+}
+static inline u32 sim_dma_target_phys_pci_coherent_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_dma_target_phys_pci_coherent_f(void)
+{
+        return 0x3U;
+}
+static inline u32 sim_dma_status_s(void)
+{
+        return 1U;
+}
+static inline u32 sim_dma_status_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 sim_dma_status_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 sim_dma_status_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 sim_dma_status_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_status_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_status__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_status__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_status__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_status__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_status_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_status_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_dma_status_valid_f(void)
+{
+        return 0x8U;
+}
+static inline u32 sim_dma_size_s(void)
+{
+        return 2U;
+}
+static inline u32 sim_dma_size_f(u32 v)
+{
+        return (v & 0x3U) << 4U;
+}
+static inline u32 sim_dma_size_m(void)
+{
+        return 0x3U << 4U;
+}
+static inline u32 sim_dma_size_v(u32 r)
+{
+        return (r >> 4U) & 0x3U;
+}
+static inline u32 sim_dma_size_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_size_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_size__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_size__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_size__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_size__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_size_4kb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_size_4kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_size_8kb_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 sim_dma_size_8kb_f(void)
+{
+        return 0x10U;
+}
+static inline u32 sim_dma_size_12kb_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 sim_dma_size_12kb_f(void)
+{
+        return 0x20U;
+}
+static inline u32 sim_dma_size_16kb_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 sim_dma_size_16kb_f(void)
+{
+        return 0x30U;
+}
+static inline u32 sim_dma_addr_lo_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_dma_addr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 sim_dma_addr_lo_m(void)
+{
+        return 0xfffffU << 12U;
+}
+static inline u32 sim_dma_addr_lo_v(u32 r)
+{
+        return (r >> 12U) & 0xfffffU;
+}
+static inline u32 sim_dma_addr_lo__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_addr_lo__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_addr_lo__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_addr_lo__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_hi_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 sim_dma_hi_addr_s(void)
+{
+        return 20U;
+}
+static inline u32 sim_dma_hi_addr_f(u32 v)
+{
+        return (v & 0xfffffU) << 0U;
+}
+static inline u32 sim_dma_hi_addr_m(void)
+{
+        return 0xfffffU << 0U;
+}
+static inline u32 sim_dma_hi_addr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 sim_dma_hi_addr__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_hi_addr__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_dma_hi_addr__prod_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_dma_hi_addr__prod_f(void)
+{
+        return 0x0U;
+}
+static inline u32 sim_msg_header_version_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_msg_header_version_major_tot_v(void)
+{
+        return 0x03000000U;
+}
+static inline u32 sim_msg_header_version_minor_tot_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_msg_signature_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 sim_msg_signature_valid_v(void)
+{
+        return 0x43505256U;
+}
+static inline u32 sim_msg_length_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 sim_msg_function_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 sim_msg_function_sim_escape_read_v(void)
+{
+        return 0x00000023U;
+}
+static inline u32 sim_msg_function_sim_escape_write_v(void)
+{
+        return 0x00000024U;
+}
+static inline u32 sim_msg_result_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 sim_msg_result_success_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 sim_msg_result_rpc_pending_v(void)
+{
+        return 0xFFFFFFFFU;
+}
+static inline u32 sim_msg_sequence_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 sim_msg_spare_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 sim_msg_spare__init_v(void)
+{
+        return 0x00000000U;
+}
+
+#endif /* __hw_sim_pci_h__ */
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c
index c19ced7c..bb44efbc 100644
--- a/drivers/gpu/nvgpu/common/linux/pci.c
+++ b/drivers/gpu/nvgpu/common/linux/pci.c
@@ -34,6 +34,8 @@
 #include "sysfs.h"
 #include "os_linux.h"
 #include "platform_gk20a.h"
+#include "sim.h"
+#include "sim_pci.h"
 
 #include "pci.h"
 #include "pci_usermode.h"
@@ -493,6 +495,10 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev)
                 goto fail;
         }
 
+        err = nvgpu_pci_init_sim_support(g);
+        if (err)
+                goto fail;
+
         nvgpu_pci_init_usermode_support(l);
 
         return 0;
diff --git a/drivers/gpu/nvgpu/common/linux/sim_pci.c b/drivers/gpu/nvgpu/common/linux/sim_pci.c
new file mode 100644
index 00000000..889eeb24
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/sim_pci.c
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/io.h>
+#include <linux/highmem.h>
+#include <linux/platform_device.h>
+
+#include <nvgpu/log.h>
+#include <nvgpu/linux/vm.h>
+
+#include "gk20a/gk20a.h"
+#include "os_linux.h"
+#include "sim.h"
+#include "hw_sim_pci.h"
+
+static inline void sim_writel(struct sim_gk20a_linux *sim_linux, u32 r, u32 v)
+{
+        writel(v, sim_linux->regs + r);
+}
+
+static inline u32 sim_readl(struct sim_gk20a_linux *sim_linux, u32 r)
+{
+        return readl(sim_linux->regs + r);
+}
+
+static void kunmap_and_free_iopage(void **kvaddr, struct page **page)
+{
+        if (*kvaddr) {
+                kunmap(*kvaddr);
+                *kvaddr = NULL;
+        }
+        if (*page) {
+                __free_page(*page);
+                *page = NULL;
+        }
+}
+
+static void gk20a_free_sim_support(struct gk20a *g)
+{
+        struct sim_gk20a_linux *sim_linux =
+                container_of(g->sim, struct sim_gk20a_linux, sim);
+        /* free sim mappings, bfrs */
+        kunmap_and_free_iopage(&sim_linux->send_bfr.kvaddr,
+                               &sim_linux->send_bfr.page);
+
+        kunmap_and_free_iopage(&sim_linux->recv_bfr.kvaddr,
+                               &sim_linux->recv_bfr.page);
+
+        kunmap_and_free_iopage(&sim_linux->msg_bfr.kvaddr,
+                               &sim_linux->msg_bfr.page);
+}
+
+static void gk20a_remove_sim_support(struct sim_gk20a *s)
+{
+        struct gk20a *g = s->g;
+        struct sim_gk20a_linux *sim_linux =
+                container_of(g->sim, struct sim_gk20a_linux, sim);
+
+        if (sim_linux->regs)
+                sim_writel(sim_linux, sim_config_r(), sim_config_mode_disabled_v());
+        gk20a_free_sim_support(g);
+
+        if (sim_linux->regs) {
+                iounmap(sim_linux->regs);
+                sim_linux->regs = NULL;
+        }
+
+        nvgpu_kfree(g, sim_linux);
+        g->sim = NULL;
+}
+
+static int alloc_and_kmap_iopage(struct gk20a *g,
+                                 void **kvaddr,
+                                 u64 *phys,
+                                 struct page **page)
+{
+        int err = 0;
+        *page = alloc_page(GFP_KERNEL);
+
+        if (!*page) {
+                err = -ENOMEM;
+                nvgpu_err(g, "couldn't allocate io page");
+                goto fail;
+        }
+
+        *kvaddr = kmap(*page);
+        if (!*kvaddr) {
+                err = -ENOMEM;
+                nvgpu_err(g, "couldn't kmap io page");
+                goto fail;
+        }
+        *phys = page_to_phys(*page);
+        return 0;
+
+ fail:
+        kunmap_and_free_iopage(kvaddr, page);
+        return err;
+
+}
+
+static inline u32 sim_msg_header_size(void)
+{
+        return 32U;
+}
+
+static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
+{
+        struct sim_gk20a_linux *sim_linux =
+                container_of(g->sim, struct sim_gk20a_linux, sim);
+        return (u32 *)(sim_linux->msg_bfr.kvaddr + byte_offset);
+}
+
+static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
+{
+        return sim_msg_bfr(g, byte_offset); /* starts at 0 */
+}
+
+static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
+{
+        /* starts after msg header/cmn */
+        return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
+}
+
+static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
+{
+        *sim_msg_hdr(g, sim_msg_header_version_r()) =
+                sim_msg_header_version_major_tot_v() |
+                sim_msg_header_version_minor_tot_v();
+        *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
+        *sim_msg_hdr(g, sim_msg_result_r())    = sim_msg_result_rpc_pending_v();
+        *sim_msg_hdr(g, sim_msg_spare_r())     = sim_msg_spare__init_v();
+        *sim_msg_hdr(g, sim_msg_function_r())  = func;
+        *sim_msg_hdr(g, sim_msg_length_r())    = size + sim_msg_header_size();
+}
+
+static inline u32 sim_escape_read_hdr_size(void)
+{
+        return 12U;
+}
+
+static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
+{
+        struct sim_gk20a_linux *sim_linux =
+                container_of(g->sim, struct sim_gk20a_linux, sim);
+        return (u32 *)(sim_linux->send_bfr.kvaddr + byte_offset);
+}
+
+static int rpc_send_message(struct gk20a *g)
+{
+        /* calculations done in units of u32s */
+        u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2;
+        u32 dma_offset = send_base + sim_dma_r()/sizeof(u32);
+        u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32);
+        struct sim_gk20a_linux *sim_linux =
+                container_of(g->sim, struct sim_gk20a_linux, sim);
+
+        *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) =
+                sim_dma_target_phys_pci_coherent_f() |
+                sim_dma_status_valid_f() |
+                sim_dma_size_4kb_f() |
+                sim_dma_addr_lo_f(sim_linux->msg_bfr.phys >> PAGE_SHIFT);
+
+        *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
+                u64_hi32(sim_linux->msg_bfr.phys);
+
+        *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
+
+        g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32)) %
+                PAGE_SIZE;
+
+        /* Update the put pointer. This will trap into the host. */
+        sim_writel(sim_linux, sim_send_put_r(), g->sim->send_ring_put);
+
+        return 0;
+}
+
+static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset)
+{
+        struct sim_gk20a_linux *sim_linux =
+                container_of(g->sim, struct sim_gk20a_linux, sim);
+        return (u32 *)(sim_linux->recv_bfr.kvaddr + byte_offset);
+}
+
+static int rpc_recv_poll(struct gk20a *g)
+{
+        u64 recv_phys_addr;
+        struct sim_gk20a_linux *sim_linux =
+                container_of(g->sim, struct sim_gk20a_linux, sim);
+
+        /* Poll the recv ring get pointer in an infinite loop */
+        do {
+                g->sim->recv_ring_put = sim_readl(sim_linux, sim_recv_put_r());
+        } while (g->sim->recv_ring_put == g->sim->recv_ring_get);
+
+        /* process all replies */
+        while (g->sim->recv_ring_put != g->sim->recv_ring_get) {
+                /* these are in u32 offsets */
+                u32 dma_lo_offset =
+                        sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0;
+                u32 dma_hi_offset = dma_lo_offset + 1;
+                u32 recv_phys_addr_lo = sim_dma_addr_lo_v(
+                                *sim_recv_ring_bfr(g, dma_lo_offset*4));
+                u32 recv_phys_addr_hi = sim_dma_hi_addr_v(
+                                *sim_recv_ring_bfr(g, dma_hi_offset*4));
+
+                recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
+                                 (u64)recv_phys_addr_lo << PAGE_SHIFT;
+
+                if (recv_phys_addr != sim_linux->msg_bfr.phys) {
+                        nvgpu_err(g, "Error in RPC reply");
+                        return -EINVAL;
+                }
+
+                /* Update GET pointer */
+                g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32)) %
+                        PAGE_SIZE;
+
+                sim_writel(sim_linux, sim_recv_get_r(), g->sim->recv_ring_get);
+
+                g->sim->recv_ring_put = sim_readl(sim_linux, sim_recv_put_r());
+        }
+
+        return 0;
+}
+
+static int issue_rpc_and_wait(struct gk20a *g)
+{
+        int err;
+
+        err = rpc_send_message(g);
+        if (err) {
+                nvgpu_err(g, "failed rpc_send_message");
+                return err;
+        }
+
+        err = rpc_recv_poll(g);
+        if (err) {
+                nvgpu_err(g, "failed rpc_recv_poll");
+                return err;
+        }
+
+        /* Now check if RPC really succeeded */
+        if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) {
+                nvgpu_err(g, "received failed status!");
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data)
+{
+        int err;
+        size_t pathlen = strlen(path);
+        u32 data_offset;
+
+        sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
+                      sim_escape_read_hdr_size());
+        *sim_msg_param(g, 0) = index;
+        *sim_msg_param(g, 4) = sizeof(u32);
+        data_offset = roundup(pathlen + 1, sizeof(u32));
+        *sim_msg_param(g, 8) = data_offset;
+        strcpy((char *)sim_msg_param(g, 0xc), path);
+
+        err = issue_rpc_and_wait(g);
+
+        if (!err)
+                memcpy(data, sim_msg_param(g, data_offset + 0xc), sizeof(u32));
+        return err;
+}
+
+static bool _nvgpu_pci_is_simulation(struct gk20a *g, u32 sim_base)
+{
+        u32 cfg;
+        bool is_simulation = false;
+
+        cfg = nvgpu_readl(g, sim_base + sim_config_r());
+        if (sim_config_mode_v(cfg) == sim_config_mode_enabled_v())
+                is_simulation = true;
+
+        return is_simulation;
+}
+
+int nvgpu_pci_init_sim_support(struct gk20a *g)
+{
+        int err = 0;
+        u64 phys;
+        struct sim_gk20a_linux *sim_linux;
+        bool is_simulation;
+        struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+
+        /* initialize sim aperture */
+        is_simulation = _nvgpu_pci_is_simulation(g, sim_r());
+        __nvgpu_set_enabled(g, NVGPU_IS_FMODEL, is_simulation);
+
+        if (!is_simulation)
+                return 0;
+
+        sim_linux = nvgpu_kzalloc(g, sizeof(*sim_linux));
+        if (!sim_linux)
+                goto fail;
+
+        g->sim = &sim_linux->sim;
+        sim_linux->regs = l->regs + sim_r();
+
+        /* allocate sim event/msg buffers */
+        err = alloc_and_kmap_iopage(g, &sim_linux->send_bfr.kvaddr,
+                                    &sim_linux->send_bfr.phys,
+                                    &sim_linux->send_bfr.page);
+
+        err = err || alloc_and_kmap_iopage(g, &sim_linux->recv_bfr.kvaddr,
+                                           &sim_linux->recv_bfr.phys,
+                                           &sim_linux->recv_bfr.page);
+
+        err = err || alloc_and_kmap_iopage(g, &sim_linux->msg_bfr.kvaddr,
+                                           &sim_linux->msg_bfr.phys,
+                                           &sim_linux->msg_bfr.page);
+
+        if (!(sim_linux->send_bfr.kvaddr && sim_linux->recv_bfr.kvaddr &&
+              sim_linux->msg_bfr.kvaddr)) {
+                nvgpu_err(g, "couldn't allocate all sim buffers");
+                goto fail;
+        }
+
+        /* mark send ring invalid */
+        sim_writel(sim_linux, sim_send_ring_r(), sim_send_ring_status_invalid_f());
+
+        /* read get pointer and make equal to put */
+        g->sim->send_ring_put = sim_readl(sim_linux, sim_send_get_r());
+        sim_writel(sim_linux, sim_send_put_r(), g->sim->send_ring_put);
+
+        /* write send ring address and make it valid */
+        phys = sim_linux->send_bfr.phys;
+        sim_writel(sim_linux, sim_send_ring_hi_r(),
+                   sim_send_ring_hi_addr_f(u64_hi32(phys)));
+        sim_writel(sim_linux, sim_send_ring_r(),
+                   sim_send_ring_status_valid_f() |
+                   sim_send_ring_target_phys_pci_coherent_f() |
+                   sim_send_ring_size_4kb_f() |
+                   sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT));
+
+        /* repeat for recv ring (but swap put,get as roles are opposite) */
+        sim_writel(sim_linux, sim_recv_ring_r(), sim_recv_ring_status_invalid_f());
+
+        /* read put pointer and make equal to get */
+        g->sim->recv_ring_get = sim_readl(sim_linux, sim_recv_put_r());
+        sim_writel(sim_linux, sim_recv_get_r(), g->sim->recv_ring_get);
+
+        /* write send ring address and make it valid */
+        phys = sim_linux->recv_bfr.phys;
+        sim_writel(sim_linux, sim_recv_ring_hi_r(),
+                   sim_recv_ring_hi_addr_f(u64_hi32(phys)));
+        sim_writel(sim_linux, sim_recv_ring_r(),
+                   sim_recv_ring_status_valid_f() |
+                   sim_recv_ring_target_phys_pci_coherent_f() |
+                   sim_recv_ring_size_4kb_f() |
+                   sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT));
+
+        g->sim->remove_support = gk20a_remove_sim_support;
+        g->sim->esc_readl = gk20a_sim_esc_readl;
+        return 0;
+
+ fail:
+        gk20a_free_sim_support(g);
+        return err;
+}
diff --git a/drivers/gpu/nvgpu/common/linux/sim_pci.h b/drivers/gpu/nvgpu/common/linux/sim_pci.h
new file mode 100644
index 00000000..22a3169c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/sim_pci.h
@@ -0,0 +1,28 @@
+/*
+ *
+ * GK20A sim support
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SIM_PCI_LINUX_H__
+#define __SIM_PCI_LINUX_H__
+
+#include "gk20a/sim_gk20a.h"
+#include "sim.h"
+
+int nvgpu_pci_init_sim_support(struct gk20a *g);
+
+#endif