diff options
author | Alex Waterman <alexw@nvidia.com> | 2016-04-27 14:06:18 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-29 17:46:55 -0400 |
commit | c8da7546432015e9fe22f9cfa326983dabaf2419 (patch) | |
tree | da8887f57258a73c4d01e9a3546fa4f77a718b5f | |
parent | a4ca63f4332a50e3fd2108d01ce452c0e607a216 (diff) |
gpu: nvgpu: Clear FIFO intr before processing finished jobs
Clear the FIFO interrupt before prcessing the job list after
receiving a nonstalling interrupt. This prevents a race in which
some non-stalling interrupts after a semaphore incr can get lost.
Bug 1732449
JIRA DNVGPU-12
Change-Id: I03df56b2ebca4ed8a0aeb26dd5480c91ffb42d8b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1133791
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index e69fb288..66dfa48a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1738,13 +1738,6 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev, | |||
1738 | return handled; | 1738 | return handled; |
1739 | } | 1739 | } |
1740 | 1740 | ||
1741 | static u32 fifo_channel_isr(struct gk20a *g, u32 fifo_intr) | ||
1742 | { | ||
1743 | gk20a_channel_semaphore_wakeup(g, false); | ||
1744 | return fifo_intr_0_channel_intr_pending_f(); | ||
1745 | } | ||
1746 | |||
1747 | |||
1748 | static u32 fifo_pbdma_isr(struct gk20a *g, u32 fifo_intr) | 1741 | static u32 fifo_pbdma_isr(struct gk20a *g, u32 fifo_intr) |
1749 | { | 1742 | { |
1750 | struct device *dev = dev_from_gk20a(g); | 1743 | struct device *dev = dev_from_gk20a(g); |
@@ -1810,10 +1803,12 @@ void gk20a_fifo_nonstall_isr(struct gk20a *g) | |||
1810 | gk20a_dbg(gpu_dbg_intr, "fifo nonstall isr %08x\n", fifo_intr); | 1803 | gk20a_dbg(gpu_dbg_intr, "fifo nonstall isr %08x\n", fifo_intr); |
1811 | 1804 | ||
1812 | if (fifo_intr & fifo_intr_0_channel_intr_pending_f()) | 1805 | if (fifo_intr & fifo_intr_0_channel_intr_pending_f()) |
1813 | clear_intr |= fifo_channel_isr(g, fifo_intr); | 1806 | clear_intr = fifo_intr_0_channel_intr_pending_f(); |
1814 | 1807 | ||
1815 | gk20a_writel(g, fifo_intr_0_r(), clear_intr); | 1808 | gk20a_writel(g, fifo_intr_0_r(), clear_intr); |
1816 | 1809 | ||
1810 | gk20a_channel_semaphore_wakeup(g, false); | ||
1811 | |||
1817 | return; | 1812 | return; |
1818 | } | 1813 | } |
1819 | 1814 | ||