gpu: nvgpu: initialize czf_bypass only once

We right now initialize czf_bypass value in gr_gp10b_init_preemption_state()
which is run at every rail ungate
And that results in any user specified value through sysfs getting lost after
railgate

To fix this, move initialization of czf_bypass to gk20a_init_gr_setup_sw() so
that it gets initialized only once
Add new HAL g->ops.gr.init_czf_bypass to initialize same and define it for
gp10b/gp106/vgpu-gp10b

Bug 2008262

Change-Id: I80a38ef527c86e32c6d64d0626b867239db9ea51
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585224
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

7 files changed, 13 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 9c09e85f..4f3b34b8 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -414,6 +414,7 @@ struct gpu_ops {
                 u32 (*tpc_enabled_exceptions)(struct gk20a *g);
                 int (*set_czf_bypass)(struct gk20a *g,
                                       struct channel_gk20a *ch);
+                void (*init_czf_bypass)(struct gk20a *g);
                 bool (*sm_debugger_attached)(struct gk20a *g);
                 void (*suspend_single_sm)(struct gk20a *g,
                                 u32 gpc, u32 tpc, u32 sm,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 6d370250..5910c7d9 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4838,6 +4838,9 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g)
 
         gr_gk20a_load_zbc_default_table(g, gr);
 
+        if (g->ops.gr.init_czf_bypass)
+                g->ops.gr.init_czf_bypass(g);
+
         nvgpu_mutex_init(&gr->ctx_mutex);
         nvgpu_spinlock_init(&gr->ch_tlb_lock);
 
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 59f72e13..b6f5a4cd 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -349,6 +349,7 @@ static const struct gpu_ops gp106_ops = {
                 .set_boosted_ctx = NULL,
                 .set_preemption_mode = gr_gp10b_set_preemption_mode,
                 .set_czf_bypass = gr_gp10b_set_czf_bypass,
+                .init_czf_bypass = gr_gp10b_init_czf_bypass,
                 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
                 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
                 .init_preemption_state = NULL,
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 060cc9fb..813b8891 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -2361,8 +2361,6 @@ int gr_gp10b_init_preemption_state(struct gk20a *g)
                         gr_debug_2_gfxp_wfi_always_injects_wfi_enabled_f());
         gk20a_writel(g, gr_debug_2_r(), debug_2);
 
-        g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v();
-
         return 0;
 }
 
@@ -2376,6 +2374,11 @@ void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
 
 }
 
+void gr_gp10b_init_czf_bypass(struct gk20a *g)
+{
+        g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v();
+}
+
 int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch)
 {
         struct nvgpu_dbg_gpu_reg_op ops;
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 6ae4789a..9ddc0375 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -143,6 +143,7 @@ int gr_gp10b_init_preemption_state(struct gk20a *g);
 void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
                         struct nvgpu_mem *mem, u64 gpu_va);
 int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch);
+void gr_gp10b_init_czf_bypass(struct gk20a *g);
 void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem);
 
 struct gr_t18x {
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index a10df740..98e143f0 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -303,6 +303,7 @@ static const struct gpu_ops gp10b_ops = {
                 .set_boosted_ctx = gr_gp10b_set_boosted_ctx,
                 .set_preemption_mode = gr_gp10b_set_preemption_mode,
                 .set_czf_bypass = gr_gp10b_set_czf_bypass,
+                .init_czf_bypass = gr_gp10b_init_czf_bypass,
                 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
                 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
                 .init_preemption_state = gr_gp10b_init_preemption_state,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 7f18bfe4..320aa4a5 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -203,6 +203,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .set_boosted_ctx = NULL,
                 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
                 .set_czf_bypass = gr_gp10b_set_czf_bypass,
+                .init_czf_bypass = gr_gp10b_init_czf_bypass,
                 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
                 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
                 .init_preemption_state = gr_gp10b_init_preemption_state,