diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-05-09 09:27:08 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-10 13:04:44 -0400 |
commit | c5db005b730af4a6d3d95787f5fb94ec5a2baee0 (patch) | |
tree | 0d3aab9a22651e524dc5cab9c05c77db1f9c3ba1 | |
parent | 4f40637c580c5f25f34f45c2c16b5332104897bc (diff) |
gpu: nvgpu: remove access to mc_enable_pb_r()
We don't need to configure mc_enable_pb_r() register in any of the supported
chips, so remove access to this register
Jira NVGPUT-52
Change-Id: I8a7a524367ce7953f926143242c6d63bc8fd5ed1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1711245
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 7 |
2 files changed, 0 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index cc63c3b8..0c3e8039 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -796,12 +796,6 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
796 | g->ops.clock_gating.blcg_fifo_load_gating_prod(g, | 796 | g->ops.clock_gating.blcg_fifo_load_gating_prod(g, |
797 | g->blcg_enabled); | 797 | g->blcg_enabled); |
798 | 798 | ||
799 | /* enable pbdma */ | ||
800 | mask = 0; | ||
801 | for (i = 0; i < host_num_pbdma; ++i) | ||
802 | mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); | ||
803 | gk20a_writel(g, mc_enable_pb_r(), mask); | ||
804 | |||
805 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); | 799 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); |
806 | timeout = set_field(timeout, fifo_fb_timeout_period_m(), | 800 | timeout = set_field(timeout, fifo_fb_timeout_period_m(), |
807 | fifo_fb_timeout_period_max_f()); | 801 | fifo_fb_timeout_period_max_f()); |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 932e7626..b374e517 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1171,13 +1171,6 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | |||
1171 | g->ops.clock_gating.blcg_fifo_load_gating_prod(g, | 1171 | g->ops.clock_gating.blcg_fifo_load_gating_prod(g, |
1172 | g->blcg_enabled); | 1172 | g->blcg_enabled); |
1173 | 1173 | ||
1174 | /* enable pbdma */ | ||
1175 | mask = 0; | ||
1176 | for (i = 0; i < host_num_pbdma; ++i) | ||
1177 | mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); | ||
1178 | gk20a_writel(g, mc_enable_pb_r(), mask); | ||
1179 | |||
1180 | |||
1181 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); | 1174 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); |
1182 | nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); | 1175 | nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); |
1183 | if (!nvgpu_platform_is_silicon(g)) { | 1176 | if (!nvgpu_platform_is_silicon(g)) { |