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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-01-25 18:08:45 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-01-26 17:12:22 -0500
commitc05cfcb576a96c8239201c71627f348b1ad79670 (patch)
tree92a16b293d5c9da0aea83071a42c093438a5f6a4
parente52c6ac1f2a8abfd51f933598b6368711c42a9fa (diff)
gpu: nvgpu: gp106: Generate new gp106 headers
Hardware headers have been outdated. Regenerate with newest tool. At the same time correct the incorrect usage of fuse fields. JIRA DNVGPU-172 Change-Id: If190bf0cf2e41d525e6ea374a30efd1f63963e5e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294267 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
-rw-r--r--drivers/gpu/nvgpu/clk/clk_vin.c47
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h26
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h78
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h6
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h96
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h10
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h18
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h57
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h30
9 files changed, 268 insertions, 100 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c
index e2a209ee..1ababe55 100644
--- a/drivers/gpu/nvgpu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/clk/clk_vin.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -43,7 +43,7 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g,
43 43
44static u32 read_vin_cal_fuse_rev(struct gk20a *g) 44static u32 read_vin_cal_fuse_rev(struct gk20a *g)
45{ 45{
46 return fuse_vin_cal_fuse_rev_v( 46 return fuse_vin_cal_fuse_rev_data_v(
47 gk20a_readl(g, fuse_vin_cal_fuse_rev_r())); 47 gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
48} 48}
49 49
@@ -103,9 +103,11 @@ static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
103 if (data == 0xFFFFFFFF) 103 if (data == 0xFFFFFFFF)
104 return -EINVAL; 104 return -EINVAL;
105 105
106 gpc0interceptdata = fuse_vin_cal_gpc0_icpt_data_v(gpc0data) * 1000; 106 gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) <<
107 gpc0interceptdata = gpc0interceptdata >> 107 fuse_vin_cal_gpc0_icpt_frac_data_s()) +
108 fuse_vin_cal_gpc0_icpt_frac_size_v(); 108 fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data);
109 gpc0interceptdata = (gpc0interceptdata * 1000U) >>
110 fuse_vin_cal_gpc0_icpt_frac_data_s();
109 111
110 switch (vin_id) { 112 switch (vin_id) {
111 case CTRL_CLK_VIN_ID_GPC0: 113 case CTRL_CLK_VIN_ID_GPC0:
@@ -119,33 +121,36 @@ static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
119 case CTRL_CLK_VIN_ID_SYS: 121 case CTRL_CLK_VIN_ID_SYS:
120 case CTRL_CLK_VIN_ID_XBAR: 122 case CTRL_CLK_VIN_ID_XBAR:
121 case CTRL_CLK_VIN_ID_LTC: 123 case CTRL_CLK_VIN_ID_LTC:
122 interceptdata = 124 interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) <<
123 (fuse_vin_cal_gpc1_icpt_data_v(data)) * 1000; 125 fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) +
124 interceptdata = interceptdata >> 126 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data);
125 fuse_vin_cal_gpc1_icpt_frac_size_v(); 127 interceptdata = (interceptdata * 1000U) >>
128 fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
126 break; 129 break;
127 130
128 case CTRL_CLK_VIN_ID_SRAM: 131 case CTRL_CLK_VIN_ID_SRAM:
129 interceptdata = 132 interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) <<
130 (fuse_vin_cal_sram_icpt_data_v(data)) * 1000; 133 fuse_vin_cal_sram_delta_icpt_frac_data_s()) +
131 interceptdata = interceptdata >> 134 fuse_vin_cal_sram_delta_icpt_frac_data_v(data);
132 fuse_vin_cal_sram_icpt_frac_size_v(); 135 interceptdata = (interceptdata * 1000U) >>
136 fuse_vin_cal_sram_delta_icpt_frac_data_s();
133 break; 137 break;
134 138
135 default: 139 default:
136 return -EINVAL; 140 return -EINVAL;
137 } 141 }
138 142
139 if (data & fuse_vin_cal_gpc1_icpt_sign_f()) 143 if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data))
140 *intercept = gpc0interceptdata - interceptdata; 144 *intercept = gpc0interceptdata - interceptdata;
141 else 145 else
142 *intercept = gpc0interceptdata + interceptdata; 146 *intercept = gpc0interceptdata + interceptdata;
143 147
144 /* slope */ 148 /* slope */
145 gpc0slopedata = (fuse_vin_cal_gpc0_slope_data_v(gpc0data)) * 1000; 149 gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) <<
146 gpc0slopedata = gpc0slopedata >> 150 fuse_vin_cal_gpc0_slope_frac_data_s()) +
147 fuse_vin_cal_gpc0_slope_frac_size_v(); 151 fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data);
148 152 gpc0slopedata = (gpc0slopedata * 1000U) >>
153 fuse_vin_cal_gpc0_slope_frac_data_s();
149 switch (vin_id) { 154 switch (vin_id) {
150 case CTRL_CLK_VIN_ID_GPC0: 155 case CTRL_CLK_VIN_ID_GPC0:
151 break; 156 break;
@@ -160,16 +165,14 @@ static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
160 case CTRL_CLK_VIN_ID_LTC: 165 case CTRL_CLK_VIN_ID_LTC:
161 case CTRL_CLK_VIN_ID_SRAM: 166 case CTRL_CLK_VIN_ID_SRAM:
162 slopedata = 167 slopedata =
163 (fuse_vin_cal_gpc1_slope_data_v(data)) * 1000; 168 (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000;
164 slopedata = slopedata >>
165 fuse_vin_cal_gpc1_slope_frac_size_v();
166 break; 169 break;
167 170
168 default: 171 default:
169 return -EINVAL; 172 return -EINVAL;
170 } 173 }
171 174
172 if (data & fuse_vin_cal_gpc1_slope_sign_f()) 175 if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data))
173 *slope = gpc0slopedata - slopedata; 176 *slope = gpc0slopedata - slopedata;
174 else 177 else
175 *slope = gpc0slopedata + slopedata; 178 *slope = gpc0slopedata + slopedata;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h
index 6d80b6a6..8b5859bf 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -50,6 +50,30 @@
50#ifndef _hw_bus_gp106_h_ 50#ifndef _hw_bus_gp106_h_
51#define _hw_bus_gp106_h_ 51#define _hw_bus_gp106_h_
52 52
53static inline u32 bus_bar0_window_r(void)
54{
55 return 0x00001700;
56}
57static inline u32 bus_bar0_window_base_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 bus_bar0_window_target_vid_mem_f(void)
62{
63 return 0x0;
64}
65static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
66{
67 return 0x2000000;
68}
69static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
70{
71 return 0x3000000;
72}
73static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
74{
75 return 0x00000010;
76}
53static inline u32 bus_bar1_block_r(void) 77static inline u32 bus_bar1_block_r(void)
54{ 78{
55 return 0x00001704; 79 return 0x00001704;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
index 519679f5..1248e0f3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -504,95 +504,75 @@ static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
504} 504}
505static inline u32 fb_fbpa_fbio_delay_r(void) 505static inline u32 fb_fbpa_fbio_delay_r(void)
506{ 506{
507 return 0x9a065c; 507 return 0x009a065c;
508}
509static inline u32 fb_fbpa_fbio_delay_src_f(u32 v)
510{
511 return (v & 0xf) << 0;
508} 512}
509static inline u32 fb_fbpa_fbio_delay_src_m(void) 513static inline u32 fb_fbpa_fbio_delay_src_m(void)
510{ 514{
511 return 0x7; 515 return 0xf << 0;
512} 516}
513static inline u32 fb_fbpa_fbio_delay_src_v(u32 r) 517static inline u32 fb_fbpa_fbio_delay_src_v(u32 r)
514{ 518{
515 return (r >> 0) & 0x7; 519 return (r >> 0) & 0xf;
516} 520}
517static inline u32 fb_fbpa_fbio_delay_src_f(u32 v) 521static inline u32 fb_fbpa_fbio_delay_src_max_v(void)
518{ 522{
519 return (v & 0x7) << 0; 523 return 0x00000002;
520} 524}
521static inline u32 fb_fbpa_fbio_delay_src_max_v(void) 525static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v)
522{ 526{
523 return 2; 527 return (v & 0xf) << 4;
524} 528}
525static inline u32 fb_fbpa_fbio_delay_priv_m(void) 529static inline u32 fb_fbpa_fbio_delay_priv_m(void)
526{ 530{
527 return 0x7 << 4; 531 return 0xf << 4;
528} 532}
529static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r) 533static inline u32 fb_fbpa_fbio_delay_priv_v(u32 r)
530{ 534{
531 return (r >> 4) & 0x7; 535 return (r >> 4) & 0xf;
532}
533static inline u32 fb_fbpa_fbio_delay_priv_f(u32 v)
534{
535 return (v & 0x7) << 4;
536} 536}
537static inline u32 fb_fbpa_fbio_delay_priv_max_v(void) 537static inline u32 fb_fbpa_fbio_delay_priv_max_v(void)
538{ 538{
539 return 2; 539 return 0x00000002;
540} 540}
541static inline u32 fb_fbpa_fbio_cmd_delay_r(void) 541static inline u32 fb_fbpa_fbio_cmd_delay_r(void)
542{ 542{
543 return 0x9a08e0; 543 return 0x009a08e0;
544}
545static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v)
546{
547 return (v & 0xf) << 0;
544} 548}
545static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void) 549static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_m(void)
546{ 550{
547 return 0x7; 551 return 0xf << 0;
548} 552}
549static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r) 553static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_v(u32 r)
550{ 554{
551 return (r >> 0) & 0x7; 555 return (r >> 0) & 0xf;
552} 556}
553static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_f(u32 v) 557static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void)
554{ 558{
555 return (v & 0x7) << 0; 559 return 0x00000001;
556} 560}
557static inline u32 fb_fbpa_fbio_cmd_delay_cmd_src_max_v(void) 561static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v)
558{ 562{
559 return 1; 563 return (v & 0xf) << 4;
560} 564}
561static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void) 565static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_m(void)
562{ 566{
563 return 0x7 << 4; 567 return 0xf << 4;
564} 568}
565static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r) 569static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_v(u32 r)
566{ 570{
567 return (r >> 4) & 0x7; 571 return (r >> 4) & 0xf;
568}
569static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_f(u32 v)
570{
571 return (v & 0x7) << 4;
572} 572}
573static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void) 573static inline u32 fb_fbpa_fbio_cmd_delay_cmd_priv_max_v(void)
574{ 574{
575 return 1; 575 return 0x00000001;
576}
577static inline u32 fb_niso_scrubber_status_r(void)
578{
579 return 0x00100b20;
580}
581static inline u32 fb_niso_scrubber_status_flag_s(void)
582{
583 return 1;
584}
585static inline u32 fb_niso_scrubber_status_flag_f(u32 v)
586{
587 return (v & 0x1) << 0;
588}
589static inline u32 fb_niso_scrubber_status_flag_m(void)
590{
591 return 0x1 << 0;
592}
593static inline u32 fb_niso_scrubber_status_flag_v(u32 r)
594{
595 return (r >> 0) & 0x1;
596} 576}
597static inline u32 fb_niso_scrub_status_r(void) 577static inline u32 fb_niso_scrub_status_r(void)
598{ 578{
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h
index ec02257e..b1b1cfcd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -326,6 +326,10 @@ static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
326{ 326{
327 return (v & 0x1) << (0 + i*1); 327 return (v & 0x1) << (0 + i*1);
328} 328}
329static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
330{
331 return (r >> (0 + i*1)) & 0x1;
332}
329static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) 333static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
330{ 334{
331 return 0x00000004; 335 return 0x00000004;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
index 32d8a4f2..4a5292bc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -124,64 +124,104 @@ static inline u32 fuse_status_opt_fbp_r(void)
124} 124}
125static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) 125static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
126{ 126{
127 return (r >> (0 + i*0)) & 0x1; 127 return (r >> (0 + i*1)) & 0x1;
128} 128}
129static inline u32 fuse_vin_cal_fuse_rev_r(void) 129static inline u32 fuse_vin_cal_fuse_rev_r(void)
130{ 130{
131 return 0x0002164c; 131 return 0x0002164c;
132} 132}
133static inline u32 fuse_vin_cal_fuse_rev_v(u32 r) 133static inline u32 fuse_vin_cal_fuse_rev_data_v(u32 r)
134{ 134{
135 return 0x3 & r; 135 return (r >> 0) & 0x3;
136} 136}
137static inline u32 fuse_vin_cal_gpc0_r(void) 137static inline u32 fuse_vin_cal_gpc0_r(void)
138{ 138{
139 return 0x00021650; 139 return 0x00021650;
140} 140}
141static inline u32 fuse_vin_cal_gpc0_icpt_data_v(u32 r) 141static inline u32 fuse_vin_cal_gpc0_icpt_int_data_s(void)
142{
143 return 12;
144}
145static inline u32 fuse_vin_cal_gpc0_icpt_int_data_v(u32 r)
142{ 146{
143 return ((r & 0xFFFC000) >> 14); 147 return (r >> 16) & 0xfff;
144} 148}
145static inline u32 fuse_vin_cal_gpc0_icpt_frac_size_v(void) 149static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_s(void)
146{ 150{
147 return 2; 151 return 2;
148} 152}
149static inline u32 fuse_vin_cal_gpc0_slope_data_v(u32 r) 153static inline u32 fuse_vin_cal_gpc0_icpt_frac_data_v(u32 r)
154{
155 return (r >> 14) & 0x3;
156}
157static inline u32 fuse_vin_cal_gpc0_slope_int_data_s(void)
158{
159 return 4;
160}
161static inline u32 fuse_vin_cal_gpc0_slope_int_data_v(u32 r)
150{ 162{
151 return (r & 0x3FFF); 163 return (r >> 10) & 0xf;
152} 164}
153static inline u32 fuse_vin_cal_gpc0_slope_frac_size_v(void) 165static inline u32 fuse_vin_cal_gpc0_slope_frac_data_s(void)
154{ 166{
155 return 10; 167 return 10;
156} 168}
169static inline u32 fuse_vin_cal_gpc0_slope_frac_data_v(u32 r)
170{
171 return (r >> 0) & 0x3ff;
172}
157static inline u32 fuse_vin_cal_gpc1_delta_r(void) 173static inline u32 fuse_vin_cal_gpc1_delta_r(void)
158{ 174{
159 return 0x00021654; 175 return 0x00021654;
160} 176}
161static inline u32 fuse_vin_cal_gpc1_icpt_sign_f(void) 177static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_s(void)
162{ 178{
163 return 0x400000; 179 return 8;
164} 180}
165static inline u32 fuse_vin_cal_gpc1_slope_sign_f(void) 181static inline u32 fuse_vin_cal_gpc1_delta_icpt_int_data_v(u32 r)
166{ 182{
167 return 0x800; 183 return (r >> 14) & 0xff;
168} 184}
169static inline u32 fuse_vin_cal_gpc1_icpt_data_v(u32 r) 185static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_s(void)
170{ 186{
171 return ((r & 0x3FF000) >> 12); 187 return 2;
172} 188}
173static inline u32 fuse_vin_cal_gpc1_icpt_frac_size_v(void) 189static inline u32 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(u32 r)
174{ 190{
175 return 2; 191 return (r >> 12) & 0x3;
192}
193static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_s(void)
194{
195 return 1;
196}
197static inline u32 fuse_vin_cal_gpc1_delta_icpt_sign_data_v(u32 r)
198{
199 return (r >> 22) & 0x1;
200}
201static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_s(void)
202{
203 return 1;
176} 204}
177static inline u32 fuse_vin_cal_gpc1_slope_data_v(u32 r) 205static inline u32 fuse_vin_cal_gpc1_delta_slope_int_data_v(u32 r)
178{ 206{
179 return (r & 0x7FF); 207 return (r >> 10) & 0x1;
180} 208}
181static inline u32 fuse_vin_cal_gpc1_slope_frac_size_v(void) 209static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_s(void)
182{ 210{
183 return 10; 211 return 10;
184} 212}
213static inline u32 fuse_vin_cal_gpc1_delta_slope_frac_data_v(u32 r)
214{
215 return (r >> 0) & 0x3ff;
216}
217static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_s(void)
218{
219 return 1;
220}
221static inline u32 fuse_vin_cal_gpc1_delta_slope_sign_data_v(u32 r)
222{
223 return (r >> 11) & 0x1;
224}
185static inline u32 fuse_vin_cal_gpc2_delta_r(void) 225static inline u32 fuse_vin_cal_gpc2_delta_r(void)
186{ 226{
187 return 0x00021658; 227 return 0x00021658;
@@ -206,12 +246,20 @@ static inline u32 fuse_vin_cal_sram_delta_r(void)
206{ 246{
207 return 0x0002166c; 247 return 0x0002166c;
208} 248}
209static inline u32 fuse_vin_cal_sram_icpt_data_v(u32 r) 249static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_s(void)
210{ 250{
211 return ((r & 0x3FF000) >> 12); 251 return 9;
212} 252}
213static inline u32 fuse_vin_cal_sram_icpt_frac_size_v(void) 253static inline u32 fuse_vin_cal_sram_delta_icpt_int_data_v(u32 r)
254{
255 return (r >> 13) & 0x1ff;
256}
257static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_s(void)
214{ 258{
215 return 1; 259 return 1;
216} 260}
261static inline u32 fuse_vin_cal_sram_delta_icpt_frac_data_v(u32 r)
262{
263 return (r >> 12) & 0x1;
264}
217#endif 265#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h
index 96ab77df..1033761b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void)
242{ 242{
243 return 0; 243 return 0;
244} 244}
245static inline u32 gmmu_new_pte_address_vid_f(u32 v)
246{
247 return (v & 0xffffff) << 8;
248}
249static inline u32 gmmu_new_pte_address_vid_w(void)
250{
251 return 0;
252}
245static inline u32 gmmu_new_pte_vol_w(void) 253static inline u32 gmmu_new_pte_vol_w(void)
246{ 254{
247 return 0; 255 return 0;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
index bb1f9fa9..22b1142f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -2090,10 +2090,22 @@ static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
2090{ 2090{
2091 return 0x00405b60 + i*4; 2091 return 0x00405b60 + i*4;
2092} 2092}
2093static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
2094{
2095 return 4;
2096}
2093static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) 2097static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
2094{ 2098{
2095 return (v & 0xf) << 0; 2099 return (v & 0xf) << 0;
2096} 2100}
2101static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
2102{
2103 return 4;
2104}
2105static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
2106{
2107 return (v & 0xf) << 4;
2108}
2097static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) 2109static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
2098{ 2110{
2099 return (v & 0xf) << 8; 2111 return (v & 0xf) << 8;
@@ -2102,6 +2114,10 @@ static inline u32 gr_cwd_sm_id_r(u32 i)
2102{ 2114{
2103 return 0x00405ba0 + i*4; 2115 return 0x00405ba0 + i*4;
2104} 2116}
2117static inline u32 gr_cwd_sm_id__size_1_v(void)
2118{
2119 return 0x00000010;
2120}
2105static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) 2121static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
2106{ 2122{
2107 return (v & 0xff) << 0; 2123 return (v & 0xff) << 0;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h
new file mode 100644
index 00000000..da1c7e68
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pram_gp106.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pram_gp106_h_
51#define _hw_pram_gp106_h_
52
53static inline u32 pram_data032_r(u32 i)
54{
55 return 0x00700000 + i*4;
56}
57#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h
index 85350954..a96659cf 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_top_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -154,6 +154,14 @@ static inline u32 top_device_info_type_enum_copy0_f(void)
154{ 154{
155 return 0x4; 155 return 0x4;
156} 156}
157static inline u32 top_device_info_type_enum_copy2_v(void)
158{
159 return 0x00000003;
160}
161static inline u32 top_device_info_type_enum_copy2_f(void)
162{
163 return 0xc;
164}
157static inline u32 top_device_info_type_enum_lce_v(void) 165static inline u32 top_device_info_type_enum_lce_v(void)
158{ 166{
159 return 0x00000013; 167 return 0x00000013;
@@ -162,6 +170,22 @@ static inline u32 top_device_info_type_enum_lce_f(void)
162{ 170{
163 return 0x4c; 171 return 0x4c;
164} 172}
173static inline u32 top_device_info_engine_v(u32 r)
174{
175 return (r >> 5) & 0x1;
176}
177static inline u32 top_device_info_runlist_v(u32 r)
178{
179 return (r >> 4) & 0x1;
180}
181static inline u32 top_device_info_intr_v(u32 r)
182{
183 return (r >> 3) & 0x1;
184}
185static inline u32 top_device_info_reset_v(u32 r)
186{
187 return (r >> 2) & 0x1;
188}
165static inline u32 top_device_info_entry_v(u32 r) 189static inline u32 top_device_info_entry_v(u32 r)
166{ 190{
167 return (r >> 0) & 0x3; 191 return (r >> 0) & 0x3;
@@ -174,6 +198,10 @@ static inline u32 top_device_info_entry_enum_v(void)
174{ 198{
175 return 0x00000002; 199 return 0x00000002;
176} 200}
201static inline u32 top_device_info_entry_engine_type_v(void)
202{
203 return 0x00000003;
204}
177static inline u32 top_device_info_entry_data_v(void) 205static inline u32 top_device_info_entry_data_v(void)
178{ 206{
179 return 0x00000001; 207 return 0x00000001;