diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-11-19 08:14:44 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:19 -0400 |
commit | bf9f5f82d185469558cefcdc9159ead09114251f (patch) | |
tree | cea7348aa8301db4163e2cfa5b299f5750a1e966 | |
parent | 2d71d633cf754e15c5667215c44086080c7c328d (diff) |
gpu: nvgpu: Use driver-wide timeout for ACR boot
In simulation we disable timeouts system-wide. Use the system-wide
timeout for ACR boot to enable ACR boot in simulation.
Bug 1546850
Change-Id: I58fc0485725195feab24ae5fe4f249116668bbcc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606273
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index cb874a48..7c6b734b 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -29,7 +29,6 @@ | |||
29 | /*Defines*/ | 29 | /*Defines*/ |
30 | #define gm20b_dbg_pmu(fmt, arg...) \ | 30 | #define gm20b_dbg_pmu(fmt, arg...) \ |
31 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 31 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
32 | #define GPU_TIMEOUT_DEFAULT 10000 | ||
33 | 32 | ||
34 | typedef int (*get_ucode_details)(struct gk20a *g, struct flcn_ucode_img *udata); | 33 | typedef int (*get_ucode_details)(struct gk20a *g, struct flcn_ucode_img *udata); |
35 | 34 | ||
@@ -1275,7 +1274,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1275 | * to PMU halt | 1274 | * to PMU halt |
1276 | */ | 1275 | */ |
1277 | 1276 | ||
1278 | if (clear_halt_interrupt_status(g, GPU_TIMEOUT_DEFAULT)) | 1277 | if (clear_halt_interrupt_status(g, gk20a_get_gr_idle_timeout(g))) |
1279 | goto err_unmap_bl; | 1278 | goto err_unmap_bl; |
1280 | 1279 | ||
1281 | gm20b_dbg_pmu("err reg :%x\n", readl(mc + | 1280 | gm20b_dbg_pmu("err reg :%x\n", readl(mc + |
@@ -1287,10 +1286,10 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1287 | gm20b_init_pmu_setup_hw1(g, desc, acr->hsbl_ucode.size); | 1286 | gm20b_init_pmu_setup_hw1(g, desc, acr->hsbl_ucode.size); |
1288 | /* Poll for HALT */ | 1287 | /* Poll for HALT */ |
1289 | if (b_wait_for_halt) { | 1288 | if (b_wait_for_halt) { |
1290 | err = pmu_wait_for_halt(g, GPU_TIMEOUT_DEFAULT); | 1289 | err = pmu_wait_for_halt(g, gk20a_get_gr_idle_timeout(g)); |
1291 | if (err == 0) { | 1290 | if (err == 0) { |
1292 | /* Clear the HALT interrupt */ | 1291 | /* Clear the HALT interrupt */ |
1293 | if (clear_halt_interrupt_status(g, GPU_TIMEOUT_DEFAULT)) | 1292 | if (clear_halt_interrupt_status(g, gk20a_get_gr_idle_timeout(g))) |
1294 | goto err_unmap_bl; | 1293 | goto err_unmap_bl; |
1295 | } | 1294 | } |
1296 | else | 1295 | else |