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authorDeepak Nibade <dnibade@nvidia.com>2014-05-28 10:11:13 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:10:16 -0400
commitbea937a74ede83ff3973b52d684ffdfabaa33767 (patch)
tree0c5a5c3dadd2d36ac3798f2d3a63cec03409b718
parente6eb4b59f6e8753c64133a4b86c6278ceef98e93 (diff)
gpu: nvgpu: add accessors for runlist ram entry
Add accessors to modify contents of runlist ram (RAMRL) entry. Using these accessors we can modify a runlist entry to specify it as regular channel or TSG entry Bug 1470692 Change-Id: If39759941ecb07af11152dbddb6fb5a67c14b26e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/416611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Randy Spurlock <rspurlock@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h42
1 files changed, 41 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h
index 7eff3881..a039685e 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -386,4 +386,44 @@ static inline u32 ram_rl_entry_size_v(void)
386{ 386{
387 return 0x00000008; 387 return 0x00000008;
388} 388}
389static inline u32 ram_rl_entry_chid_f(u32 v)
390{
391 return (v & 0xfff) << 0;
392}
393static inline u32 ram_rl_entry_id_f(u32 v)
394{
395 return (v & 0xfff) << 0;
396}
397static inline u32 ram_rl_entry_type_f(u32 v)
398{
399 return (v & 0x1) << 13;
400}
401static inline u32 ram_rl_entry_type_chid_f(void)
402{
403 return 0x0;
404}
405static inline u32 ram_rl_entry_type_tsg_f(void)
406{
407 return 0x2000;
408}
409static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
410{
411 return (v & 0xf) << 14;
412}
413static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
414{
415 return 0xc000;
416}
417static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
418{
419 return (v & 0xff) << 18;
420}
421static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
422{
423 return 0x2000000;
424}
425static inline u32 ram_rl_entry_tsg_length_f(u32 v)
426{
427 return (v & 0x3f) << 26;
428}
389#endif 429#endif