gpu: nvgpu: Add HALs to implement pdb cache WAR

We have a h/w bug on some chips and we need to support below additional
HALs to implement a s/w WAR
gops.fifo.init_pdb_cache_war()
gops.fifo.deinit_pdb_cache_war()
gops.fb.apply_pdb_cache_war()

Add new API nvgpu_init_mm_pdb_cache_war() to initialize WAR sequence
and call this from MM initialization and before setting up rest of the
memory management units
Deinitialize WAR while cleaning up MM support

Add pdb_cache_war_mem member to gk20a to hold all the memory needed
for the WAR

Bug 200449545

Change-Id: Id2ac0d940c7881c7b0cf396413273c0f329a1a1f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1834901
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 35 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c
index 88e3baa8..6c8f2cdf 100644
--- a/drivers/gpu/nvgpu/common/mm/mm.c
+++ b/drivers/gpu/nvgpu/common/mm/mm.c
@@ -198,6 +198,10 @@ static void nvgpu_remove_mm_support(struct mm_gk20a *mm)
         nvgpu_semaphore_sea_destroy(g);
         nvgpu_vidmem_destroy(g);
         nvgpu_pd_cache_fini(g);
+
+        if (g->ops.fifo.deinit_pdb_cache_war) {
+                g->ops.fifo.deinit_pdb_cache_war(g);
+        }
 }
 
 /* pmu vm, share channel_vm interfaces */
@@ -501,6 +505,27 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g)
         return 0;
 }
 
+static int nvgpu_init_mm_pdb_cache_war(struct gk20a *g)
+{
+        int err;
+
+        if (g->ops.fifo.init_pdb_cache_war) {
+                err = g->ops.fifo.init_pdb_cache_war(g);
+                if (err) {
+                        return err;
+                }
+        }
+
+        if (g->ops.fb.apply_pdb_cache_war) {
+                err = g->ops.fb.apply_pdb_cache_war(g);
+                if (err) {
+                        return err;
+                }
+        }
+
+        return 0;
+}
+
 int nvgpu_init_mm_support(struct gk20a *g)
 {
         u32 err;
@@ -510,6 +535,11 @@ int nvgpu_init_mm_support(struct gk20a *g)
                 return err;
         }
 
+        err = nvgpu_init_mm_pdb_cache_war(g);
+        if (err) {
+                return err;
+        }
+
         err = nvgpu_init_mm_setup_sw(g);
         if (err) {
                 return err;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 593b553c..2fd533c6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -583,6 +583,7 @@ struct gpu_ops {
                                  u32 index, u32 state);
                 void (*fault_buf_configure_hw)(struct gk20a *g, u32 index);
                 size_t (*get_vidmem_size)(struct gk20a *g);
+                int (*apply_pdb_cache_war)(struct gk20a *g);
         } fb;
         struct {
                 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
@@ -749,6 +750,8 @@ struct gpu_ops {
                         struct nvgpu_semaphore *s, u64 sema_va,
                         struct priv_cmd_entry *cmd,
                         u32 off, bool acquire, bool wfi);
+                int (*init_pdb_cache_war)(struct gk20a *g);
+                void (*deinit_pdb_cache_war)(struct gk20a *g);
         } fifo;
         struct pmu_v {
                 u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);
@@ -1647,6 +1650,8 @@ struct gk20a {
 
         struct nvgpu_list_node boardobj_head;
         struct nvgpu_list_node boardobjgrp_head;
+
+        struct nvgpu_mem pdb_cache_war_mem;
 };
 
 static inline bool nvgpu_is_timeouts_enabled(struct gk20a *g)