diff options
author | Antony Clince Alex <aalex@nvidia.com> | 2018-04-25 04:12:16 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-09 21:25:36 -0400 |
commit | b144935644f76328aa9ec2592655b4553ed28222 (patch) | |
tree | 7c5883e71348743ea1ff774ab76919eb070c6068 | |
parent | 2a23cd249451c952aaab71eaad6cf5f77d2bc6e2 (diff) |
gpu: nvgpu: refactored struct sim_gk20a
moved sim buffer(send, recv and msg) from
os-specific structure to OS agnostic structure.
JIRA VQRM-2368
Change-Id: I10ff23fe24d86f2bd372f1bae0369cc45aadfb80
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702178
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/sim.c | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/sim.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/sim_pci.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/sim_gk20a.h | 5 |
4 files changed, 26 insertions, 54 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/sim.c b/drivers/gpu/nvgpu/common/linux/sim.c index 7ab7a153..8f016e58 100644 --- a/drivers/gpu/nvgpu/common/linux/sim.c +++ b/drivers/gpu/nvgpu/common/linux/sim.c | |||
@@ -75,12 +75,9 @@ static void gk20a_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem) | |||
75 | 75 | ||
76 | static void gk20a_free_sim_support(struct gk20a *g) | 76 | static void gk20a_free_sim_support(struct gk20a *g) |
77 | { | 77 | { |
78 | struct sim_gk20a_linux *sim_linux = | 78 | gk20a_free_sim_buffer(g, &g->sim->send_bfr); |
79 | container_of(g->sim, struct sim_gk20a_linux, sim); | 79 | gk20a_free_sim_buffer(g, &g->sim->recv_bfr); |
80 | 80 | gk20a_free_sim_buffer(g, &g->sim->msg_bfr); | |
81 | gk20a_free_sim_buffer(g, &sim_linux->send_bfr); | ||
82 | gk20a_free_sim_buffer(g, &sim_linux->recv_bfr); | ||
83 | gk20a_free_sim_buffer(g, &sim_linux->msg_bfr); | ||
84 | } | 81 | } |
85 | 82 | ||
86 | static void gk20a_remove_sim_support(struct sim_gk20a *s) | 83 | static void gk20a_remove_sim_support(struct sim_gk20a *s) |
@@ -91,12 +88,12 @@ static void gk20a_remove_sim_support(struct sim_gk20a *s) | |||
91 | 88 | ||
92 | if (sim_linux->regs) | 89 | if (sim_linux->regs) |
93 | sim_writel(s, sim_config_r(), sim_config_mode_disabled_v()); | 90 | sim_writel(s, sim_config_r(), sim_config_mode_disabled_v()); |
94 | gk20a_free_sim_support(g); | ||
95 | 91 | ||
96 | if (sim_linux->regs) { | 92 | if (sim_linux->regs) { |
97 | iounmap(sim_linux->regs); | 93 | iounmap(sim_linux->regs); |
98 | sim_linux->regs = NULL; | 94 | sim_linux->regs = NULL; |
99 | } | 95 | } |
96 | gk20a_free_sim_support(g); | ||
100 | 97 | ||
101 | nvgpu_kfree(g, sim_linux); | 98 | nvgpu_kfree(g, sim_linux); |
102 | g->sim = NULL; | 99 | g->sim = NULL; |
@@ -109,8 +106,6 @@ static inline u32 sim_msg_header_size(void) | |||
109 | 106 | ||
110 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) | 107 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) |
111 | { | 108 | { |
112 | struct sim_gk20a_linux *sim_linux = | ||
113 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
114 | u8 *cpu_va; | 109 | u8 *cpu_va; |
115 | 110 | ||
116 | cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va; | 111 | cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va; |
@@ -146,8 +141,6 @@ static inline u32 sim_escape_read_hdr_size(void) | |||
146 | 141 | ||
147 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) | 142 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) |
148 | { | 143 | { |
149 | struct sim_gk20a_linux *sim_linux = | ||
150 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
151 | u8 *cpu_va; | 144 | u8 *cpu_va; |
152 | 145 | ||
153 | cpu_va = (u8 *)sim_linux->send_bfr.cpu_va; | 146 | cpu_va = (u8 *)sim_linux->send_bfr.cpu_va; |
@@ -161,8 +154,6 @@ static int rpc_send_message(struct gk20a *g) | |||
161 | u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2; | 154 | u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2; |
162 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); | 155 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); |
163 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); | 156 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); |
164 | struct sim_gk20a_linux *sim_linux = | ||
165 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
166 | 157 | ||
167 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = | 158 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = |
168 | sim_dma_target_phys_pci_coherent_f() | | 159 | sim_dma_target_phys_pci_coherent_f() | |
@@ -171,7 +162,7 @@ static int rpc_send_message(struct gk20a *g) | |||
171 | sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT); | 162 | sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT); |
172 | 163 | ||
173 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | 164 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = |
174 | u64_hi32(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)); | 165 | u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr)); |
175 | 166 | ||
176 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; | 167 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; |
177 | 168 | ||
@@ -185,8 +176,6 @@ static int rpc_send_message(struct gk20a *g) | |||
185 | 176 | ||
186 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | 177 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) |
187 | { | 178 | { |
188 | struct sim_gk20a_linux *sim_linux = | ||
189 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
190 | u8 *cpu_va; | 179 | u8 *cpu_va; |
191 | 180 | ||
192 | cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va; | 181 | cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va; |
@@ -197,8 +186,6 @@ static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | |||
197 | static int rpc_recv_poll(struct gk20a *g) | 186 | static int rpc_recv_poll(struct gk20a *g) |
198 | { | 187 | { |
199 | u64 recv_phys_addr; | 188 | u64 recv_phys_addr; |
200 | struct sim_gk20a_linux *sim_linux = | ||
201 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
202 | 189 | ||
203 | /* XXX This read is not required (?) */ | 190 | /* XXX This read is not required (?) */ |
204 | /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ | 191 | /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ |
@@ -223,7 +210,7 @@ static int rpc_recv_poll(struct gk20a *g) | |||
223 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | 210 | (u64)recv_phys_addr_lo << PAGE_SHIFT; |
224 | 211 | ||
225 | if (recv_phys_addr != | 212 | if (recv_phys_addr != |
226 | nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)) { | 213 | nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) { |
227 | nvgpu_err(g, "%s Error in RPC reply", | 214 | nvgpu_err(g, "%s Error in RPC reply", |
228 | __func__); | 215 | __func__); |
229 | return -1; | 216 | return -1; |
@@ -293,13 +280,11 @@ int gk20a_init_sim_support(struct gk20a *g) | |||
293 | { | 280 | { |
294 | int err = 0; | 281 | int err = 0; |
295 | u64 phys; | 282 | u64 phys; |
296 | struct sim_gk20a_linux *sim_linux = | ||
297 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
298 | 283 | ||
299 | /* allocate sim event/msg buffers */ | 284 | /* allocate sim event/msg buffers */ |
300 | err = gk20a_alloc_sim_buffer(g, &sim_linux->send_bfr); | 285 | err = gk20a_alloc_sim_buffer(g, &g->sim->send_bfr); |
301 | err = err || gk20a_alloc_sim_buffer(g, &sim_linux->recv_bfr); | 286 | err = err || gk20a_alloc_sim_buffer(g, &g->sim->recv_bfr); |
302 | err = err || gk20a_alloc_sim_buffer(g, &sim_linux->msg_bfr); | 287 | err = err || gk20a_alloc_sim_buffer(g, &g->sim->msg_bfr); |
303 | 288 | ||
304 | if (err) | 289 | if (err) |
305 | goto fail; | 290 | goto fail; |
@@ -311,7 +296,7 @@ int gk20a_init_sim_support(struct gk20a *g) | |||
311 | sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); | 296 | sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); |
312 | 297 | ||
313 | /*write send ring address and make it valid*/ | 298 | /*write send ring address and make it valid*/ |
314 | phys = nvgpu_mem_get_addr(g, &sim_linux->send_bfr); | 299 | phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr); |
315 | sim_writel(g->sim, sim_send_ring_hi_r(), | 300 | sim_writel(g->sim, sim_send_ring_hi_r(), |
316 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | 301 | sim_send_ring_hi_addr_f(u64_hi32(phys))); |
317 | sim_writel(g->sim, sim_send_ring_r(), | 302 | sim_writel(g->sim, sim_send_ring_r(), |
@@ -328,7 +313,7 @@ int gk20a_init_sim_support(struct gk20a *g) | |||
328 | sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); | 313 | sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); |
329 | 314 | ||
330 | /*write send ring address and make it valid*/ | 315 | /*write send ring address and make it valid*/ |
331 | phys = nvgpu_mem_get_addr(g, &sim_linux->recv_bfr); | 316 | phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr); |
332 | sim_writel(g->sim, sim_recv_ring_hi_r(), | 317 | sim_writel(g->sim, sim_recv_ring_hi_r(), |
333 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | 318 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); |
334 | sim_writel(g->sim, sim_recv_ring_r(), | 319 | sim_writel(g->sim, sim_recv_ring_r(), |
diff --git a/drivers/gpu/nvgpu/common/linux/sim.h b/drivers/gpu/nvgpu/common/linux/sim.h index 4b5e910c..e800728c 100644 --- a/drivers/gpu/nvgpu/common/linux/sim.h +++ b/drivers/gpu/nvgpu/common/linux/sim.h | |||
@@ -27,9 +27,6 @@ struct sim_gk20a_linux { | |||
27 | struct sim_gk20a sim; | 27 | struct sim_gk20a sim; |
28 | struct resource *reg_mem; | 28 | struct resource *reg_mem; |
29 | void __iomem *regs; | 29 | void __iomem *regs; |
30 | struct nvgpu_mem send_bfr; | ||
31 | struct nvgpu_mem recv_bfr; | ||
32 | struct nvgpu_mem msg_bfr; | ||
33 | }; | 30 | }; |
34 | 31 | ||
35 | int gk20a_init_sim_support(struct gk20a *g); | 32 | int gk20a_init_sim_support(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/common/linux/sim_pci.c b/drivers/gpu/nvgpu/common/linux/sim_pci.c index ea417615..1ab8c57c 100644 --- a/drivers/gpu/nvgpu/common/linux/sim_pci.c +++ b/drivers/gpu/nvgpu/common/linux/sim_pci.c | |||
@@ -75,12 +75,9 @@ static void gk20a_free_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem) | |||
75 | 75 | ||
76 | static void gk20a_free_sim_support(struct gk20a *g) | 76 | static void gk20a_free_sim_support(struct gk20a *g) |
77 | { | 77 | { |
78 | struct sim_gk20a_linux *sim_linux = | 78 | gk20a_free_sim_buffer(g, &g->sim->send_bfr); |
79 | container_of(g->sim, struct sim_gk20a_linux, sim); | 79 | gk20a_free_sim_buffer(g, &g->sim->recv_bfr); |
80 | 80 | gk20a_free_sim_buffer(g, &g->sim->msg_bfr); | |
81 | gk20a_free_sim_buffer(g, &sim_linux->send_bfr); | ||
82 | gk20a_free_sim_buffer(g, &sim_linux->recv_bfr); | ||
83 | gk20a_free_sim_buffer(g, &sim_linux->msg_bfr); | ||
84 | } | 81 | } |
85 | 82 | ||
86 | static void gk20a_remove_sim_support(struct sim_gk20a *s) | 83 | static void gk20a_remove_sim_support(struct sim_gk20a *s) |
@@ -91,12 +88,12 @@ static void gk20a_remove_sim_support(struct sim_gk20a *s) | |||
91 | 88 | ||
92 | if (sim_linux->regs) | 89 | if (sim_linux->regs) |
93 | sim_writel(s, sim_config_r(), sim_config_mode_disabled_v()); | 90 | sim_writel(s, sim_config_r(), sim_config_mode_disabled_v()); |
94 | gk20a_free_sim_support(g); | ||
95 | 91 | ||
96 | if (sim_linux->regs) { | 92 | if (sim_linux->regs) { |
97 | iounmap(sim_linux->regs); | 93 | iounmap(sim_linux->regs); |
98 | sim_linux->regs = NULL; | 94 | sim_linux->regs = NULL; |
99 | } | 95 | } |
96 | gk20a_free_sim_support(g); | ||
100 | 97 | ||
101 | nvgpu_kfree(g, sim_linux); | 98 | nvgpu_kfree(g, sim_linux); |
102 | g->sim = NULL; | 99 | g->sim = NULL; |
@@ -109,8 +106,6 @@ static inline u32 sim_msg_header_size(void) | |||
109 | 106 | ||
110 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) | 107 | static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) |
111 | { | 108 | { |
112 | struct sim_gk20a_linux *sim_linux = | ||
113 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
114 | u8 *cpu_va; | 109 | u8 *cpu_va; |
115 | 110 | ||
116 | cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va; | 111 | cpu_va = (u8 *)sim_linux->msg_bfr.cpu_va; |
@@ -148,8 +143,6 @@ static inline u32 sim_escape_read_hdr_size(void) | |||
148 | 143 | ||
149 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) | 144 | static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) |
150 | { | 145 | { |
151 | struct sim_gk20a_linux *sim_linux = | ||
152 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
153 | u8 *cpu_va; | 146 | u8 *cpu_va; |
154 | 147 | ||
155 | cpu_va = (u8 *)sim_linux->send_bfr.cpu_va; | 148 | cpu_va = (u8 *)sim_linux->send_bfr.cpu_va; |
@@ -163,8 +156,6 @@ static int rpc_send_message(struct gk20a *g) | |||
163 | u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2; | 156 | u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2; |
164 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); | 157 | u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); |
165 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); | 158 | u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); |
166 | struct sim_gk20a_linux *sim_linux = | ||
167 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
168 | 159 | ||
169 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = | 160 | *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = |
170 | sim_dma_target_phys_pci_coherent_f() | | 161 | sim_dma_target_phys_pci_coherent_f() | |
@@ -173,7 +164,7 @@ static int rpc_send_message(struct gk20a *g) | |||
173 | sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT); | 164 | sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr) >> PAGE_SHIFT); |
174 | 165 | ||
175 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | 166 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = |
176 | u64_hi32(nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)); | 167 | u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr)); |
177 | 168 | ||
178 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; | 169 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; |
179 | 170 | ||
@@ -188,8 +179,6 @@ static int rpc_send_message(struct gk20a *g) | |||
188 | 179 | ||
189 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | 180 | static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) |
190 | { | 181 | { |
191 | struct sim_gk20a_linux *sim_linux = | ||
192 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
193 | u8 *cpu_va; | 182 | u8 *cpu_va; |
194 | 183 | ||
195 | cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va; | 184 | cpu_va = (u8 *)sim_linux->recv_bfr.cpu_va; |
@@ -200,8 +189,6 @@ static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) | |||
200 | static int rpc_recv_poll(struct gk20a *g) | 189 | static int rpc_recv_poll(struct gk20a *g) |
201 | { | 190 | { |
202 | u64 recv_phys_addr; | 191 | u64 recv_phys_addr; |
203 | struct sim_gk20a_linux *sim_linux = | ||
204 | container_of(g->sim, struct sim_gk20a_linux, sim); | ||
205 | 192 | ||
206 | /* Poll the recv ring get pointer in an infinite loop */ | 193 | /* Poll the recv ring get pointer in an infinite loop */ |
207 | do { | 194 | do { |
@@ -223,7 +210,7 @@ static int rpc_recv_poll(struct gk20a *g) | |||
223 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | 210 | (u64)recv_phys_addr_lo << PAGE_SHIFT; |
224 | 211 | ||
225 | if (recv_phys_addr != | 212 | if (recv_phys_addr != |
226 | nvgpu_mem_get_addr(g, &sim_linux->msg_bfr)) { | 213 | nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) { |
227 | nvgpu_err(g, "Error in RPC reply"); | 214 | nvgpu_err(g, "Error in RPC reply"); |
228 | return -EINVAL; | 215 | return -EINVAL; |
229 | } | 216 | } |
@@ -320,9 +307,9 @@ int nvgpu_pci_init_sim_support(struct gk20a *g) | |||
320 | sim_linux->regs = l->regs + sim_r(); | 307 | sim_linux->regs = l->regs + sim_r(); |
321 | 308 | ||
322 | /* allocate sim event/msg buffers */ | 309 | /* allocate sim event/msg buffers */ |
323 | err = gk20a_alloc_sim_buffer(g, &sim_linux->send_bfr); | 310 | err = gk20a_alloc_sim_buffer(g, &g->sim->send_bfr); |
324 | err = err || gk20a_alloc_sim_buffer(g, &sim_linux->recv_bfr); | 311 | err = err || gk20a_alloc_sim_buffer(g, &g->sim->recv_bfr); |
325 | err = err || gk20a_alloc_sim_buffer(g, &sim_linux->msg_bfr); | 312 | err = err || gk20a_alloc_sim_buffer(g, &g->sim->msg_bfr); |
326 | 313 | ||
327 | if (err) | 314 | if (err) |
328 | goto fail; | 315 | goto fail; |
@@ -334,7 +321,7 @@ int nvgpu_pci_init_sim_support(struct gk20a *g) | |||
334 | sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); | 321 | sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); |
335 | 322 | ||
336 | /* write send ring address and make it valid */ | 323 | /* write send ring address and make it valid */ |
337 | phys = nvgpu_mem_get_addr(g, &sim_linux->send_bfr); | 324 | phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr); |
338 | sim_writel(g->sim, sim_send_ring_hi_r(), | 325 | sim_writel(g->sim, sim_send_ring_hi_r(), |
339 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | 326 | sim_send_ring_hi_addr_f(u64_hi32(phys))); |
340 | sim_writel(g->sim, sim_send_ring_r(), | 327 | sim_writel(g->sim, sim_send_ring_r(), |
@@ -351,7 +338,7 @@ int nvgpu_pci_init_sim_support(struct gk20a *g) | |||
351 | sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); | 338 | sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); |
352 | 339 | ||
353 | /* write send ring address and make it valid */ | 340 | /* write send ring address and make it valid */ |
354 | phys = nvgpu_mem_get_addr(g, &sim_linux->recv_bfr); | 341 | phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr); |
355 | sim_writel(g->sim, sim_recv_ring_hi_r(), | 342 | sim_writel(g->sim, sim_recv_ring_hi_r(), |
356 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | 343 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); |
357 | sim_writel(g->sim, sim_recv_ring_r(), | 344 | sim_writel(g->sim, sim_recv_ring_r(), |
diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h index 8f23abd8..fb64d959 100644 --- a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GK20A sim support | 4 | * GK20A sim support |
5 | * | 5 | * |
6 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the "Software"), | 9 | * copy of this software and associated documentation files (the "Software"), |
@@ -34,6 +34,9 @@ struct sim_gk20a { | |||
34 | u32 recv_ring_get; | 34 | u32 recv_ring_get; |
35 | u32 recv_ring_put; | 35 | u32 recv_ring_put; |
36 | u32 sequence_base; | 36 | u32 sequence_base; |
37 | struct nvgpu_mem send_bfr; | ||
38 | struct nvgpu_mem recv_bfr; | ||
39 | struct nvgpu_mem msg_bfr; | ||
37 | void (*remove_support)(struct sim_gk20a *); | 40 | void (*remove_support)(struct sim_gk20a *); |
38 | int (*esc_readl)( | 41 | int (*esc_readl)( |
39 | struct gk20a *g, char *path, u32 index, u32 *data); | 42 | struct gk20a *g, char *path, u32 index, u32 *data); |