diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-03-31 16:33:02 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-13 16:12:41 -0400 |
commit | 9b5427da37161c350d28a821652f2bb84bca360f (patch) | |
tree | 989e7b649b7b5e54d1d316b245b61c1881a15de6 | |
parent | 2adf9164d9d68cc3ab700af84724034682f44ab8 (diff) |
gpu: nvgpu: Support GPUs with no physical mode
Support GPUs which cannot choose between SMMU and physical
addressing.
Change-Id: If3256fa1bc795a84d039ad3aa63ebdccf5cc0afb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120469
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 16 |
12 files changed, 59 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 61211239..e8d82e0e 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -333,33 +333,32 @@ static int channel_gk20a_setup_userd(struct channel_gk20a *c) | |||
333 | return 0; | 333 | return 0; |
334 | } | 334 | } |
335 | 335 | ||
336 | static void channel_gk20a_bind(struct channel_gk20a *ch_gk20a) | 336 | static void channel_gk20a_bind(struct channel_gk20a *c) |
337 | { | 337 | { |
338 | struct gk20a *g = ch_gk20a->g; | 338 | struct gk20a *g = c->g; |
339 | struct fifo_gk20a *f = &g->fifo; | 339 | struct fifo_gk20a *f = &g->fifo; |
340 | struct fifo_engine_info_gk20a *engine_info = | 340 | struct fifo_engine_info_gk20a *engine_info = |
341 | f->engine_info + ENGINE_GR_GK20A; | 341 | f->engine_info + ENGINE_GR_GK20A; |
342 | 342 | u32 inst_ptr = gk20a_mm_inst_block_addr(g, &c->inst_block) | |
343 | u32 inst_ptr = gk20a_mem_phys(&ch_gk20a->inst_block) | ||
344 | >> ram_in_base_shift_v(); | 343 | >> ram_in_base_shift_v(); |
345 | 344 | ||
346 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", | 345 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", |
347 | ch_gk20a->hw_chid, inst_ptr); | 346 | c->hw_chid, inst_ptr); |
348 | 347 | ||
349 | ch_gk20a->bound = true; | 348 | c->bound = true; |
350 | 349 | ||
351 | gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid), | 350 | gk20a_writel(g, ccsr_channel_r(c->hw_chid), |
352 | (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) & | 351 | (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & |
353 | ~ccsr_channel_runlist_f(~0)) | | 352 | ~ccsr_channel_runlist_f(~0)) | |
354 | ccsr_channel_runlist_f(engine_info->runlist_id)); | 353 | ccsr_channel_runlist_f(engine_info->runlist_id)); |
355 | 354 | ||
356 | gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid), | 355 | gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), |
357 | ccsr_channel_inst_ptr_f(inst_ptr) | | 356 | ccsr_channel_inst_ptr_f(inst_ptr) | |
358 | ccsr_channel_inst_target_vid_mem_f() | | 357 | ccsr_channel_inst_target_vid_mem_f() | |
359 | ccsr_channel_inst_bind_true_f()); | 358 | ccsr_channel_inst_bind_true_f()); |
360 | 359 | ||
361 | gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid), | 360 | gk20a_writel(g, ccsr_channel_r(c->hw_chid), |
362 | (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) & | 361 | (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & |
363 | ~ccsr_channel_enable_set_f(~0)) | | 362 | ~ccsr_channel_enable_set_f(~0)) | |
364 | ccsr_channel_enable_set_true_f()); | 363 | ccsr_channel_enable_set_true_f()); |
365 | } | 364 | } |
@@ -402,7 +401,7 @@ int channel_gk20a_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) | |||
402 | return err; | 401 | return err; |
403 | 402 | ||
404 | gk20a_dbg_info("channel %d inst block physical addr: 0x%16llx", | 403 | gk20a_dbg_info("channel %d inst block physical addr: 0x%16llx", |
405 | ch->hw_chid, (u64)gk20a_mem_phys(&ch->inst_block)); | 404 | ch->hw_chid, gk20a_mm_inst_block_addr(g, &ch->inst_block)); |
406 | 405 | ||
407 | gk20a_dbg_fn("done"); | 406 | gk20a_dbg_fn("done"); |
408 | return 0; | 407 | return 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c index 3fb003bf..2008289b 100644 --- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | |||
@@ -281,7 +281,7 @@ static int css_hw_enable_snapshot(struct gr_gk20a *gr, u32 snapshot_size) | |||
281 | gk20a_writel(g, perf_pmasys_outsize_r(), snapshot_size); | 281 | gk20a_writel(g, perf_pmasys_outsize_r(), snapshot_size); |
282 | 282 | ||
283 | /* this field is aligned to 4K */ | 283 | /* this field is aligned to 4K */ |
284 | inst_pa_page = gk20a_mem_phys(&g->mm.hwpm.inst_block) >> 12; | 284 | inst_pa_page = gk20a_mm_inst_block_addr(g, &g->mm.hwpm.inst_block) >> 12; |
285 | 285 | ||
286 | /* A write to MEM_BLOCK triggers the block bind operation. MEM_BLOCK | 286 | /* A write to MEM_BLOCK triggers the block bind operation. MEM_BLOCK |
287 | * should be written last */ | 287 | * should be written last */ |
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 309fe75a..95957788 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -1046,7 +1046,7 @@ static int gk20a_perfbuf_map(struct dbg_session_gk20a *dbg_s, | |||
1046 | gk20a_writel(g, perf_pmasys_outsize_r(), virt_size); | 1046 | gk20a_writel(g, perf_pmasys_outsize_r(), virt_size); |
1047 | 1047 | ||
1048 | /* this field is aligned to 4K */ | 1048 | /* this field is aligned to 4K */ |
1049 | inst_pa_page = gk20a_mem_phys(&g->mm.hwpm.inst_block) >> 12; | 1049 | inst_pa_page = gk20a_mm_inst_block_addr(g, &g->mm.hwpm.inst_block) >> 12; |
1050 | 1050 | ||
1051 | /* A write to MEM_BLOCK triggers the block bind operation. MEM_BLOCK | 1051 | /* A write to MEM_BLOCK triggers the block bind operation. MEM_BLOCK |
1052 | * should be written last */ | 1052 | * should be written last */ |
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 58d8fda1..f9cddc41 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -624,12 +624,13 @@ static int gk20a_fecs_trace_bind_channel(struct gk20a *g, | |||
624 | 624 | ||
625 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, | 625 | gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, |
626 | "hw_chid=%d context_ptr=%x inst_block=%llx", | 626 | "hw_chid=%d context_ptr=%x inst_block=%llx", |
627 | ch->hw_chid, context_ptr, gk20a_mem_phys(&ch->inst_block)); | 627 | ch->hw_chid, context_ptr, |
628 | gk20a_mm_inst_block_addr(g, &ch->inst_block)); | ||
628 | 629 | ||
629 | if (!trace) | 630 | if (!trace) |
630 | return -ENOMEM; | 631 | return -ENOMEM; |
631 | 632 | ||
632 | pa = gk20a_mem_phys(&trace->trace_buf); | 633 | pa = gk20a_mm_inst_block_addr(g, &trace->trace_buf); |
633 | if (!pa) | 634 | if (!pa) |
634 | return -ENOMEM; | 635 | return -ENOMEM; |
635 | 636 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 4422bca4..44329a53 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -654,17 +654,21 @@ int gk20a_init_fifo_support(struct gk20a *g) | |||
654 | static struct channel_gk20a * | 654 | static struct channel_gk20a * |
655 | channel_from_inst_ptr(struct fifo_gk20a *f, u64 inst_ptr) | 655 | channel_from_inst_ptr(struct fifo_gk20a *f, u64 inst_ptr) |
656 | { | 656 | { |
657 | struct gk20a *g = f->g; | ||
657 | int ci; | 658 | int ci; |
658 | if (unlikely(!f->channel)) | 659 | if (unlikely(!f->channel)) |
659 | return NULL; | 660 | return NULL; |
660 | for (ci = 0; ci < f->num_channels; ci++) { | 661 | for (ci = 0; ci < f->num_channels; ci++) { |
661 | struct channel_gk20a *ch = gk20a_channel_get(&f->channel[ci]); | 662 | struct channel_gk20a *ch; |
663 | u64 ch_inst_ptr; | ||
664 | |||
665 | ch = gk20a_channel_get(&f->channel[ci]); | ||
662 | /* only alive channels are searched */ | 666 | /* only alive channels are searched */ |
663 | if (!ch) | 667 | if (!ch) |
664 | continue; | 668 | continue; |
665 | 669 | ||
666 | if (ch->inst_block.cpu_va && | 670 | ch_inst_ptr = gk20a_mm_inst_block_addr(g, &ch->inst_block); |
667 | (inst_ptr == gk20a_mem_phys(&ch->inst_block))) | 671 | if (ch->inst_block.cpu_va && inst_ptr == ch_inst_ptr) |
668 | return ch; | 672 | return ch; |
669 | 673 | ||
670 | gk20a_channel_put(ch); | 674 | gk20a_channel_put(ch); |
@@ -1087,10 +1091,10 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1087 | ch->hw_chid); | 1091 | ch->hw_chid); |
1088 | } | 1092 | } |
1089 | } else if (f.inst_ptr == | 1093 | } else if (f.inst_ptr == |
1090 | gk20a_mem_phys(&g->mm.bar1.inst_block)) { | 1094 | gk20a_mm_inst_block_addr(g, &g->mm.bar1.inst_block)) { |
1091 | gk20a_err(dev_from_gk20a(g), "mmu fault from bar1"); | 1095 | gk20a_err(dev_from_gk20a(g), "mmu fault from bar1"); |
1092 | } else if (f.inst_ptr == | 1096 | } else if (f.inst_ptr == |
1093 | gk20a_mem_phys(&g->mm.pmu.inst_block)) { | 1097 | gk20a_mm_inst_block_addr(g, &g->mm.pmu.inst_block)) { |
1094 | gk20a_err(dev_from_gk20a(g), "mmu fault from pmu"); | 1098 | gk20a_err(dev_from_gk20a(g), "mmu fault from pmu"); |
1095 | } else | 1099 | } else |
1096 | gk20a_err(dev_from_gk20a(g), "couldn't locate channel for mmu fault"); | 1100 | gk20a_err(dev_from_gk20a(g), "couldn't locate channel for mmu fault"); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index f3bf0517..1091b235 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1542,6 +1542,7 @@ static int gk20a_probe(struct platform_device *dev) | |||
1542 | gk20a->mm.ltc_enabled_debug = true; | 1542 | gk20a->mm.ltc_enabled_debug = true; |
1543 | gk20a->mm.bypass_smmu = platform->bypass_smmu; | 1543 | gk20a->mm.bypass_smmu = platform->bypass_smmu; |
1544 | gk20a->mm.disable_bigpage = platform->disable_bigpage; | 1544 | gk20a->mm.disable_bigpage = platform->disable_bigpage; |
1545 | gk20a->mm.has_physical_mode = true; | ||
1545 | gk20a->debugfs_ltc_enabled = | 1546 | gk20a->debugfs_ltc_enabled = |
1546 | debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR, | 1547 | debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR, |
1547 | platform->debugfs, | 1548 | platform->debugfs, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index ada67edd..27406f9e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -729,7 +729,7 @@ int gr_gk20a_ctx_patch_write(struct gk20a *g, | |||
729 | static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, | 729 | static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g, |
730 | struct channel_gk20a *c) | 730 | struct channel_gk20a *c) |
731 | { | 731 | { |
732 | u32 inst_base_ptr = u64_lo32(gk20a_mem_phys(&c->inst_block) | 732 | u32 inst_base_ptr = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block) |
733 | >> ram_in_base_shift_v()); | 733 | >> ram_in_base_shift_v()); |
734 | u32 ret; | 734 | u32 ret; |
735 | 735 | ||
@@ -1408,7 +1408,7 @@ static int gr_gk20a_fecs_ctx_image_save(struct channel_gk20a *c, u32 save_type) | |||
1408 | int ret; | 1408 | int ret; |
1409 | 1409 | ||
1410 | u32 inst_base_ptr = | 1410 | u32 inst_base_ptr = |
1411 | u64_lo32(gk20a_mem_phys(&c->inst_block) | 1411 | u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block) |
1412 | >> ram_in_base_shift_v()); | 1412 | >> ram_in_base_shift_v()); |
1413 | 1413 | ||
1414 | 1414 | ||
@@ -1875,7 +1875,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1875 | 1875 | ||
1876 | if (tegra_platform_is_linsim()) { | 1876 | if (tegra_platform_is_linsim()) { |
1877 | u32 inst_base_ptr = | 1877 | u32 inst_base_ptr = |
1878 | u64_lo32(gk20a_mem_phys(&c->inst_block) | 1878 | u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block) |
1879 | >> ram_in_base_shift_v()); | 1879 | >> ram_in_base_shift_v()); |
1880 | 1880 | ||
1881 | ret = gr_gk20a_submit_fecs_method_op(g, | 1881 | ret = gr_gk20a_submit_fecs_method_op(g, |
@@ -2103,7 +2103,7 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2103 | 2103 | ||
2104 | gk20a_writel(g, gr_fecs_arb_ctx_adr_r(), 0x0); | 2104 | gk20a_writel(g, gr_fecs_arb_ctx_adr_r(), 0x0); |
2105 | 2105 | ||
2106 | inst_ptr = gk20a_mem_phys(&ucode_info->inst_blk_desc); | 2106 | inst_ptr = gk20a_mm_inst_block_addr(g, &ucode_info->inst_blk_desc); |
2107 | gk20a_writel(g, gr_fecs_new_ctx_r(), | 2107 | gk20a_writel(g, gr_fecs_new_ctx_r(), |
2108 | gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | | 2108 | gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | |
2109 | gr_fecs_new_ctx_target_m() | | 2109 | gr_fecs_new_ctx_target_m() | |
@@ -4712,7 +4712,7 @@ static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g) | |||
4712 | 4712 | ||
4713 | 4713 | ||
4714 | err = gr_gk20a_fecs_set_reglist_bind_inst(g, | 4714 | err = gr_gk20a_fecs_set_reglist_bind_inst(g, |
4715 | gk20a_mem_phys(&mm->pmu.inst_block)); | 4715 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block)); |
4716 | if (err) { | 4716 | if (err) { |
4717 | gk20a_err(dev_from_gk20a(g), | 4717 | gk20a_err(dev_from_gk20a(g), |
4718 | "fail to bind pmu inst to gr"); | 4718 | "fail to bind pmu inst to gr"); |
@@ -4991,7 +4991,7 @@ int gk20a_gr_reset(struct gk20a *g) | |||
4991 | } | 4991 | } |
4992 | 4992 | ||
4993 | err = gr_gk20a_fecs_set_reglist_bind_inst(g, | 4993 | err = gr_gk20a_fecs_set_reglist_bind_inst(g, |
4994 | gk20a_mem_phys(&g->mm.pmu.inst_block)); | 4994 | gk20a_mm_inst_block_addr(g, &g->mm.pmu.inst_block)); |
4995 | if (err) { | 4995 | if (err) { |
4996 | gk20a_err(dev_from_gk20a(g), | 4996 | gk20a_err(dev_from_gk20a(g), |
4997 | "fail to bind pmu inst to gr"); | 4997 | "fail to bind pmu inst to gr"); |
@@ -5372,7 +5372,7 @@ static struct channel_gk20a *gk20a_gr_get_channel_from_ctx( | |||
5372 | if (!gk20a_channel_get(ch)) | 5372 | if (!gk20a_channel_get(ch)) |
5373 | continue; | 5373 | continue; |
5374 | 5374 | ||
5375 | if ((u32)(gk20a_mem_phys(&ch->inst_block) >> | 5375 | if ((u32)(gk20a_mm_inst_block_addr(g, &ch->inst_block) >> |
5376 | ram_in_base_shift_v()) == | 5376 | ram_in_base_shift_v()) == |
5377 | gr_fecs_current_ctx_ptr_v(curr_ctx)) { | 5377 | gr_fecs_current_ctx_ptr_v(curr_ctx)) { |
5378 | tsgid = ch->tsgid; | 5378 | tsgid = ch->tsgid; |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index ac4625e0..519faeeb 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -482,7 +482,7 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) | |||
482 | { | 482 | { |
483 | struct mm_gk20a *mm = &g->mm; | 483 | struct mm_gk20a *mm = &g->mm; |
484 | struct mem_desc *inst_block = &mm->bar1.inst_block; | 484 | struct mem_desc *inst_block = &mm->bar1.inst_block; |
485 | phys_addr_t inst_pa = gk20a_mem_phys(inst_block); | 485 | u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); |
486 | int err; | 486 | int err; |
487 | 487 | ||
488 | gk20a_dbg_fn(""); | 488 | gk20a_dbg_fn(""); |
@@ -2249,7 +2249,7 @@ void gk20a_free_sgtable(struct sg_table **sgt) | |||
2249 | 2249 | ||
2250 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova) | 2250 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova) |
2251 | { | 2251 | { |
2252 | if (!device_is_iommuable(dev_from_gk20a(g))) | 2252 | if (!device_is_iommuable(dev_from_gk20a(g)) || !g->mm.has_physical_mode) |
2253 | return iova; | 2253 | return iova; |
2254 | else | 2254 | else |
2255 | return iova | 1ULL << g->ops.mm.get_physical_addr_bits(g); | 2255 | return iova | 1ULL << g->ops.mm.get_physical_addr_bits(g); |
@@ -3382,6 +3382,17 @@ void gk20a_free_inst_block(struct gk20a *g, struct mem_desc *inst_block) | |||
3382 | gk20a_gmmu_free(g, inst_block); | 3382 | gk20a_gmmu_free(g, inst_block); |
3383 | } | 3383 | } |
3384 | 3384 | ||
3385 | u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct mem_desc *inst_block) | ||
3386 | { | ||
3387 | u64 addr; | ||
3388 | if (g->mm.has_physical_mode) | ||
3389 | addr = gk20a_mem_phys(inst_block); | ||
3390 | else | ||
3391 | addr = gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(inst_block->sgt->sgl)); | ||
3392 | |||
3393 | return addr; | ||
3394 | } | ||
3395 | |||
3385 | static int gk20a_init_bar1_vm(struct mm_gk20a *mm) | 3396 | static int gk20a_init_bar1_vm(struct mm_gk20a *mm) |
3386 | { | 3397 | { |
3387 | int err; | 3398 | int err; |
@@ -3484,11 +3495,10 @@ void gk20a_init_inst_block(struct mem_desc *inst_block, struct vm_gk20a *vm, | |||
3484 | { | 3495 | { |
3485 | struct gk20a *g = gk20a_from_vm(vm); | 3496 | struct gk20a *g = gk20a_from_vm(vm); |
3486 | u64 pde_addr = g->ops.mm.get_iova_addr(g, vm->pdb.sgt->sgl, 0); | 3497 | u64 pde_addr = g->ops.mm.get_iova_addr(g, vm->pdb.sgt->sgl, 0); |
3487 | phys_addr_t inst_pa = gk20a_mem_phys(inst_block); | ||
3488 | void *inst_ptr = inst_block->cpu_va; | 3498 | void *inst_ptr = inst_block->cpu_va; |
3489 | 3499 | ||
3490 | gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", | 3500 | gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", |
3491 | (u64)inst_pa, inst_ptr); | 3501 | gk20a_mm_inst_block_addr(g, inst_block), inst_ptr); |
3492 | 3502 | ||
3493 | gk20a_dbg_info("pde pa=0x%llx", (u64)pde_addr); | 3503 | gk20a_dbg_info("pde pa=0x%llx", (u64)pde_addr); |
3494 | 3504 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 5390536e..4482a21d 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -346,6 +346,7 @@ struct mm_gk20a { | |||
346 | #endif | 346 | #endif |
347 | u32 bypass_smmu; | 347 | u32 bypass_smmu; |
348 | u32 disable_bigpage; | 348 | u32 disable_bigpage; |
349 | bool has_physical_mode; | ||
349 | }; | 350 | }; |
350 | 351 | ||
351 | int gk20a_mm_init(struct mm_gk20a *mm); | 352 | int gk20a_mm_init(struct mm_gk20a *mm); |
@@ -420,6 +421,7 @@ int gk20a_alloc_inst_block(struct gk20a *g, struct mem_desc *inst_block); | |||
420 | void gk20a_free_inst_block(struct gk20a *g, struct mem_desc *inst_block); | 421 | void gk20a_free_inst_block(struct gk20a *g, struct mem_desc *inst_block); |
421 | void gk20a_init_inst_block(struct mem_desc *inst_block, struct vm_gk20a *vm, | 422 | void gk20a_init_inst_block(struct mem_desc *inst_block, struct vm_gk20a *vm, |
422 | u32 big_page_size); | 423 | u32 big_page_size); |
424 | u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct mem_desc *mem); | ||
423 | 425 | ||
424 | void gk20a_mm_dump_vm(struct vm_gk20a *vm, | 426 | void gk20a_mm_dump_vm(struct vm_gk20a *vm, |
425 | u64 va_begin, u64 va_end, char *label); | 427 | u64 va_begin, u64 va_end, char *label); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 3b154f30..957537a9 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -1827,7 +1827,7 @@ int pmu_bootstrap(struct pmu_gk20a *pmu) | |||
1827 | pwr_falcon_itfen_ctxen_enable_f()); | 1827 | pwr_falcon_itfen_ctxen_enable_f()); |
1828 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | 1828 | gk20a_writel(g, pwr_pmu_new_instblk_r(), |
1829 | pwr_pmu_new_instblk_ptr_f( | 1829 | pwr_pmu_new_instblk_ptr_f( |
1830 | gk20a_mem_phys(&mm->pmu.inst_block) >> 12) | | 1830 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
1831 | pwr_pmu_new_instblk_valid_f(1) | | 1831 | pwr_pmu_new_instblk_valid_f(1) | |
1832 | pwr_pmu_new_instblk_target_sys_coh_f()); | 1832 | pwr_pmu_new_instblk_target_sys_coh_f()); |
1833 | 1833 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 79f90f0b..0e6e715d 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1169,7 +1169,7 @@ static int bl_bootstrap(struct pmu_gk20a *pmu, | |||
1169 | pwr_falcon_itfen_ctxen_enable_f()); | 1169 | pwr_falcon_itfen_ctxen_enable_f()); |
1170 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | 1170 | gk20a_writel(g, pwr_pmu_new_instblk_r(), |
1171 | pwr_pmu_new_instblk_ptr_f( | 1171 | pwr_pmu_new_instblk_ptr_f( |
1172 | gk20a_mem_phys(&mm->pmu.inst_block) >> 12) | | 1172 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
1173 | pwr_pmu_new_instblk_valid_f(1) | | 1173 | pwr_pmu_new_instblk_valid_f(1) | |
1174 | pwr_pmu_new_instblk_target_sys_coh_f()); | 1174 | pwr_pmu_new_instblk_target_sys_coh_f()); |
1175 | 1175 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index b9763224..188d1781 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -20,25 +20,25 @@ | |||
20 | #include "hw_ram_gm20b.h" | 20 | #include "hw_ram_gm20b.h" |
21 | #include "hw_fifo_gm20b.h" | 21 | #include "hw_fifo_gm20b.h" |
22 | 22 | ||
23 | static void channel_gm20b_bind(struct channel_gk20a *ch_gk20a) | 23 | static void channel_gm20b_bind(struct channel_gk20a *c) |
24 | { | 24 | { |
25 | struct gk20a *g = ch_gk20a->g; | 25 | struct gk20a *g = c->g; |
26 | 26 | ||
27 | u32 inst_ptr = gk20a_mem_phys(&ch_gk20a->inst_block) | 27 | u32 inst_ptr = gk20a_mm_inst_block_addr(g, &c->inst_block) |
28 | >> ram_in_base_shift_v(); | 28 | >> ram_in_base_shift_v(); |
29 | 29 | ||
30 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", | 30 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", |
31 | ch_gk20a->hw_chid, inst_ptr); | 31 | c->hw_chid, inst_ptr); |
32 | 32 | ||
33 | ch_gk20a->bound = true; | 33 | c->bound = true; |
34 | 34 | ||
35 | gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid), | 35 | gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), |
36 | ccsr_channel_inst_ptr_f(inst_ptr) | | 36 | ccsr_channel_inst_ptr_f(inst_ptr) | |
37 | ccsr_channel_inst_target_vid_mem_f() | | 37 | ccsr_channel_inst_target_vid_mem_f() | |
38 | ccsr_channel_inst_bind_true_f()); | 38 | ccsr_channel_inst_bind_true_f()); |
39 | 39 | ||
40 | gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid), | 40 | gk20a_writel(g, ccsr_channel_r(c->hw_chid), |
41 | (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) & | 41 | (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & |
42 | ~ccsr_channel_enable_set_f(~0)) | | 42 | ~ccsr_channel_enable_set_f(~0)) | |
43 | ccsr_channel_enable_set_true_f()); | 43 | ccsr_channel_enable_set_true_f()); |
44 | } | 44 | } |