gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheable

Some of the allocated buffers are used during normal graphics
processing. Mark them as GPU cacheable to improve performance.

Bug 1695718

Change-Id: I71d5d1538516e966526abe5e38a557776321597f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/827087
(cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed)
Reviewed-on: http://git-master/r/828493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 57 insertions, 17 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index de6023b5..c801a2b8 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -18,6 +18,7 @@
 #include <linux/tegra-fuse.h>
 
 #include "gk20a/gr_gk20a.h"
+#include "gk20a/semaphore_gk20a.h"
 
 #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
 #include "gp10b/gr_gp10b.h"
@@ -492,6 +493,36 @@ static int gr_gp10b_init_ctx_state(struct gk20a *g)
         return 0;
 }
 
+int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
+                        struct mem_desc *mem)
+{
+        int err;
+
+        gk20a_dbg_fn("");
+
+        err = gk20a_gmmu_alloc_attr(vm->mm->g, 0, size, mem);
+        if (err)
+                return err;
+
+        mem->gpu_va = gk20a_gmmu_map(vm,
+                                &mem->sgt,
+                                size,
+                                NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
+                                gk20a_mem_flag_none,
+                                false);
+
+        if (!mem->gpu_va) {
+                err = -ENOMEM;
+                goto fail_free;
+        }
+
+        return 0;
+
+fail_free:
+        gk20a_gmmu_free(vm->mm->g, mem);
+        return err;
+}
+
 static int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
                           struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
                           u32 class,
@@ -530,32 +561,36 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
                 gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size);
                 gk20a_dbg_info("gfxp context attrib_cb_size=%d",
                                 attrib_cb_size);
-                err = gk20a_gmmu_alloc_map(vm, g->gr.t18x.ctx_vars.preempt_image_size,
-                                &(*gr_ctx)->t18x.preempt_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        g->gr.t18x.ctx_vars.preempt_image_size,
+                                        &(*gr_ctx)->t18x.preempt_ctxsw_buffer);
                 if (err) {
                         gk20a_err(dev_from_gk20a(vm->mm->g),
                                   "cannot allocate preempt buffer");
                         goto fail_free_gk20a_ctx;
                 }
 
-                err = gk20a_gmmu_alloc_map(vm, spill_size,
-                                &(*gr_ctx)->t18x.spill_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        spill_size,
+                                        &(*gr_ctx)->t18x.spill_ctxsw_buffer);
                 if (err) {
                         gk20a_err(dev_from_gk20a(vm->mm->g),
                                   "cannot allocate spill buffer");
                         goto fail_free_preempt;
                 }
 
-                err = gk20a_gmmu_alloc_map(vm, attrib_cb_size,
-                                           &(*gr_ctx)->t18x.betacb_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        attrib_cb_size,
+                                        &(*gr_ctx)->t18x.betacb_ctxsw_buffer);
                 if (err) {
                         gk20a_err(dev_from_gk20a(vm->mm->g),
                                   "cannot allocate beta buffer");
                         goto fail_free_spill;
                 }
 
-                err = gk20a_gmmu_alloc_map(vm, pagepool_size,
-                                           &(*gr_ctx)->t18x.pagepool_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        pagepool_size,
+                                        &(*gr_ctx)->t18x.pagepool_ctxsw_buffer);
                 if (err) {
                         gk20a_err(dev_from_gk20a(vm->mm->g),
                                   "cannot allocate page pool");
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index bf49ba6f..62b70a22 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -33,6 +33,8 @@ enum {
 #define NVC0C0_SET_SHADER_EXCEPTIONS            0x1528
 
 void gp10b_init_gr(struct gpu_ops *ops);
+int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
+                        struct mem_desc *mem);
 
 struct gr_t18x {
         struct {
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
index 5edaa819..c5c53b58 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -84,9 +84,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
                 gk20a_dbg_info("gfxp context attrib cb size=%d",
                         attrib_cb_size);
 
-                err = gk20a_gmmu_alloc_map(vm,
-                                g->gr.t18x.ctx_vars.preempt_image_size,
-                                &gr_ctx->t18x.preempt_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        g->gr.t18x.ctx_vars.preempt_image_size,
+                                        &gr_ctx->t18x.preempt_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;
@@ -95,8 +95,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
                 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
                 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
 
-                err = gk20a_gmmu_alloc_map(vm, spill_size,
-                                &gr_ctx->t18x.spill_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        spill_size,
+                                        &gr_ctx->t18x.spill_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;
@@ -105,8 +106,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
                 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
                 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
 
-                err = gk20a_gmmu_alloc_map(vm, pagepool_size,
-                                           &gr_ctx->t18x.pagepool_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        pagepool_size,
+                                        &gr_ctx->t18x.pagepool_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;
@@ -116,8 +118,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
                         desc->gpu_va;
                 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
 
-                err = gk20a_gmmu_alloc_map(vm, attrib_cb_size,
-                                           &gr_ctx->t18x.betacb_ctxsw_buffer);
+                err = gr_gp10b_alloc_buffer(vm,
+                                        attrib_cb_size,
+                                        &gr_ctx->t18x.betacb_ctxsw_buffer);
                 if (err) {
                         err = -ENOMEM;
                         goto fail;