gpu: nvgpu: support masking hww_warp_esr

Add below API pointer to support masking of hww_warp_esr
after hardware read of register and before using it
further
u32 (*mask_hww_warp_esr)(u32 hww_warp_esr)

If needed, this API will mask value of hww_warp_esr
appropriately and return it

Bug 200156699

Change-Id: I1afb1347e650fab607009c1ee55691484653a4c1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/927133
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 14 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 333f8889..2b4c3237 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -201,6 +201,7 @@ struct gpu_ops {
                                 bool sm_debugger_attached,
                                 struct channel_gk20a *fault_ch,
                                 bool *early_exit, bool *ignore_debugger);
+                u32 (*mask_hww_warp_esr)(u32 hww_warp_esr);
         } gr;
         const char *name;
         struct {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 6e3ea00a..152d3f5e 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5182,6 +5182,11 @@ void gk20a_gr_clear_sm_hww(struct gk20a *g,
                         gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f());
 }
 
+u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr)
+{
+        return hww_warp_esr;
+}
+
 static int gk20a_gr_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 bool *post_event, struct channel_gk20a *fault_ch)
 {
@@ -5206,6 +5211,7 @@ static int gk20a_gr_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
         global_esr = gk20a_readl(g,
                                  gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
         warp_esr = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset);
+        warp_esr = g->ops.gr.mask_hww_warp_esr(warp_esr);
 
         if (g->ops.gr.pre_process_sm_exception) {
                 ret = g->ops.gr.pre_process_sm_exception(g, gpc, tpc,
@@ -7009,6 +7015,9 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc,
                                 gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset);
                 u32 dbgr_status0 = gk20a_readl(g,
                                 gr_gpc0_tpc0_sm_dbgr_status0_r() + offset);
+
+                warp_esr = g->ops.gr.mask_hww_warp_esr(warp_esr);
+
                 locked_down =
                     (gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(dbgr_status0) ==
                      gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v());
@@ -7531,4 +7540,5 @@ void gk20a_init_gr_ops(struct gpu_ops *gops)
         gops->gr.bpt_reg_info = gr_gk20a_bpt_reg_info;
         gops->gr.get_access_map = gr_gk20a_get_access_map;
         gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error;
+        gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 74da0cf1..42e9fa5c 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -566,4 +566,6 @@ int gr_gk20a_get_ctx_id(struct gk20a *g,
                 struct channel_gk20a *c,
                 u32 *ctx_id);
 
+u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr);
+
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 309aaf95..74d687ec 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1227,4 +1227,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
         gops->gr.bpt_reg_info = gr_gm20b_bpt_reg_info;
         gops->gr.get_access_map = gr_gm20b_get_access_map;
         gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error;
+        gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr;
 }