diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-09 16:56:31 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-10 02:34:19 -0400 |
commit | 961e98aa11d11e46c57318cd9c8a3b4b41ede7a2 (patch) | |
tree | 3522b0670d9ec508d9456eb0b296944d90b65eda | |
parent | 0e53ae618c21a0ac21f2648346301f9e29d4d463 (diff) |
gpu: nvgpu: add gr ops for mpc exception handling
Required for t19x
JIRA GPUT19X-69
Change-Id: I96d1ee2ae1bf310ce572cb4dc7773818a42a25a0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515913
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 9 |
2 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fa1b39fd..dee74fdd 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -317,6 +317,8 @@ struct gpu_ops { | |||
317 | u32 *hww_global_esr); | 317 | u32 *hww_global_esr); |
318 | int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, | 318 | int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, |
319 | bool *post_event); | 319 | bool *post_event); |
320 | int (*handle_tpc_mpc_exception)(struct gk20a *g, | ||
321 | u32 gpc, u32 tpc, bool *post_event); | ||
320 | int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc, | 322 | int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc, |
321 | u32 gpc_exception); | 323 | u32 gpc_exception); |
322 | int (*handle_gpc_gpcmmu_exception)(struct gk20a *g, u32 gpc, | 324 | int (*handle_gpc_gpcmmu_exception)(struct gk20a *g, u32 gpc, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d853c4f0..c935809e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5634,8 +5634,9 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
5634 | + offset); | 5634 | + offset); |
5635 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); | 5635 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); |
5636 | 5636 | ||
5637 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, ""); | 5637 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, |
5638 | 5638 | "GPC%d TPC%d: pending exception 0x%x", | |
5639 | gpc, tpc, tpc_exception); | ||
5639 | 5640 | ||
5640 | /* check if an sm exeption is pending */ | 5641 | /* check if an sm exeption is pending */ |
5641 | if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) == | 5642 | if (gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(tpc_exception) == |
@@ -5682,6 +5683,10 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
5682 | ret = g->ops.gr.handle_tex_exception(g, gpc, tpc, post_event); | 5683 | ret = g->ops.gr.handle_tex_exception(g, gpc, tpc, post_event); |
5683 | } | 5684 | } |
5684 | 5685 | ||
5686 | if (g->ops.gr.handle_tpc_mpc_exception) | ||
5687 | ret = g->ops.gr.handle_tpc_mpc_exception(g, | ||
5688 | gpc, tpc, post_event); | ||
5689 | |||
5685 | return ret; | 5690 | return ret; |
5686 | } | 5691 | } |
5687 | 5692 | ||