diff options
author | Richard Zhao <rizhao@nvidia.com> | 2015-12-04 18:25:46 -0500 |
---|---|---|
committer | Vladislav Buzov <vbuzov@nvidia.com> | 2016-01-10 23:06:12 -0500 |
commit | 942936bae027cb774caaf257c22eb42be32dc2ec (patch) | |
tree | f6fecfeb859116765acf0db1aaf1fefba1f567c6 | |
parent | f1d41774627efe612ee0ef0868d7233c5f2038f3 (diff) |
gpu: nvgpu: vgpu: add set sm debug mode support
JIRA VFND-1006
Bug 1594604
Change-Id: If6eb7ae22b5b0557faddd3d68deb791abb24bec4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/923233
(cherry picked from commit 9e14ca393c3044be702c50524a9ef3a2c3a6270c)
Reviewed-on: http://git-master/r/841866
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 22 | ||||
-rw-r--r-- | include/linux/tegra_vgpu.h | 10 |
2 files changed, 31 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index d8da6f3f..835351c4 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -926,6 +926,27 @@ int vgpu_gr_nonstall_isr(struct gk20a *g, | |||
926 | return 0; | 926 | return 0; |
927 | } | 927 | } |
928 | 928 | ||
929 | static int vgpu_gr_set_sm_debug_mode(struct gk20a *g, | ||
930 | struct channel_gk20a *ch, u64 sms, bool enable) | ||
931 | { | ||
932 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
933 | struct tegra_vgpu_cmd_msg msg; | ||
934 | struct tegra_vgpu_sm_debug_mode *p = &msg.params.sm_debug_mode; | ||
935 | int err; | ||
936 | |||
937 | gk20a_dbg_fn(""); | ||
938 | |||
939 | msg.cmd = TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE; | ||
940 | msg.handle = platform->virt_handle; | ||
941 | p->handle = ch->virt_ctx; | ||
942 | p->sms = sms; | ||
943 | p->enable = (u32)enable; | ||
944 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
945 | WARN_ON(err || msg.ret); | ||
946 | |||
947 | return err ? err : msg.ret; | ||
948 | } | ||
949 | |||
929 | void vgpu_init_gr_ops(struct gpu_ops *gops) | 950 | void vgpu_init_gr_ops(struct gpu_ops *gops) |
930 | { | 951 | { |
931 | gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; | 952 | gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; |
@@ -944,4 +965,5 @@ void vgpu_init_gr_ops(struct gpu_ops *gops) | |||
944 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; | 965 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; |
945 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; | 966 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; |
946 | gops->gr.init_ctx_state = vgpu_gr_init_ctx_state; | 967 | gops->gr.init_ctx_state = vgpu_gr_init_ctx_state; |
968 | gops->gr.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode; | ||
947 | } | 969 | } |
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index b7bcc905..dbfa06d5 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -71,7 +71,8 @@ enum { | |||
71 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, | 71 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, |
72 | TEGRA_VGPU_CMD_AS_MAP_EX, | 72 | TEGRA_VGPU_CMD_AS_MAP_EX, |
73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, | 73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, |
74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE | 74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, |
75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE | ||
75 | }; | 76 | }; |
76 | 77 | ||
77 | struct tegra_vgpu_connect_params { | 78 | struct tegra_vgpu_connect_params { |
@@ -264,6 +265,12 @@ struct tegra_vgpu_mmu_debug_mode { | |||
264 | u32 enable; | 265 | u32 enable; |
265 | }; | 266 | }; |
266 | 267 | ||
268 | struct tegra_vgpu_sm_debug_mode { | ||
269 | u64 handle; | ||
270 | u64 sms; | ||
271 | u32 enable; | ||
272 | }; | ||
273 | |||
267 | struct tegra_vgpu_cmd_msg { | 274 | struct tegra_vgpu_cmd_msg { |
268 | u32 cmd; | 275 | u32 cmd; |
269 | int ret; | 276 | int ret; |
@@ -289,6 +296,7 @@ struct tegra_vgpu_cmd_msg { | |||
289 | struct tegra_vgpu_zbc_query_table_params zbc_query_table; | 296 | struct tegra_vgpu_zbc_query_table_params zbc_query_table; |
290 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; | 297 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; |
291 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; | 298 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; |
299 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | ||
292 | char padding[192]; | 300 | char padding[192]; |
293 | } params; | 301 | } params; |
294 | }; | 302 | }; |