diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-03-01 14:28:44 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-03-24 17:25:18 -0400 |
commit | 907a43831513c2863e2f7fefc2d051f396d02354 (patch) | |
tree | 0febbe5a2c80cb2392dc5a9cd15cc064f2cae705 | |
parent | 845a693d13ad4399cd85d795324dc0eb9586784e (diff) |
gpu: nvgpu: vgpu: pass pid when allocate context
Bug 1648908
Change-Id: I39b1becf0b00e930a180a5a8367c22ff4d495446
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1031860
(cherry picked from commit f1940e1438fb3494c3093f1ab6a11bed6deb2b93)
Reviewed-on: http://git-master/r/1022182
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 1 | ||||
-rw-r--r-- | include/linux/tegra_vgpu.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index e636d5ae..9e40218d 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -81,6 +81,7 @@ static int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) | |||
81 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX; | 81 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX; |
82 | msg.handle = platform->virt_handle; | 82 | msg.handle = platform->virt_handle; |
83 | p->id = ch->hw_chid; | 83 | p->id = ch->hw_chid; |
84 | p->pid = (u64)current->pid; | ||
84 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 85 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
85 | if (err || msg.ret) { | 86 | if (err || msg.ret) { |
86 | gk20a_err(dev_from_gk20a(g), "fail"); | 87 | gk20a_err(dev_from_gk20a(g), "fail"); |
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index d84d0c63..c4dd81dd 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -86,6 +86,7 @@ struct tegra_vgpu_connect_params { | |||
86 | 86 | ||
87 | struct tegra_vgpu_channel_hwctx_params { | 87 | struct tegra_vgpu_channel_hwctx_params { |
88 | u32 id; | 88 | u32 id; |
89 | u64 pid; | ||
89 | u64 handle; | 90 | u64 handle; |
90 | }; | 91 | }; |
91 | 92 | ||