diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 20:11:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:06:56 -0400 |
commit | 8fb191aec01d0b4c83fbfe12310ed7827d87a873 (patch) | |
tree | a25a113ce492fc4196cc2622a7930d50554d0744 | |
parent | 7185dcdbf8292bbdfceae49702107f0661397d21 (diff) |
gpu: nvgpu: gv11b: init resume_all_sms gr ops
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: Ia5c0a3d1dead9c6094ca28716c06929dd3461814
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512210
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f7d5eb62..0f331293 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2912,6 +2912,71 @@ static void gv11b_gr_resume_single_sm(struct gk20a *g, | |||
2912 | 2912 | ||
2913 | } | 2913 | } |
2914 | 2914 | ||
2915 | static void gv11b_gr_resume_all_sms(struct gk20a *g) | ||
2916 | { | ||
2917 | u32 dbgr_control0, dbgr_status0; | ||
2918 | /* | ||
2919 | * The following requires some clarification. Despite the fact that both | ||
2920 | * RUN_TRIGGER and STOP_TRIGGER have the word "TRIGGER" in their | ||
2921 | * names, only one is actually a trigger, and that is the STOP_TRIGGER. | ||
2922 | * Merely writing a 1(_TASK) to the RUN_TRIGGER is not sufficient to | ||
2923 | * resume the gpu - the _STOP_TRIGGER must explicitly be set to 0 | ||
2924 | * (_DISABLE) as well. | ||
2925 | |||
2926 | * Advice from the arch group: Disable the stop trigger first, as a | ||
2927 | * separate operation, in order to ensure that the trigger has taken | ||
2928 | * effect, before enabling the run trigger. | ||
2929 | */ | ||
2930 | |||
2931 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "resuming all sms"); | ||
2932 | |||
2933 | /* Read from unicast registers */ | ||
2934 | dbgr_control0 = | ||
2935 | gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); | ||
2936 | dbgr_status0 = | ||
2937 | gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_status0_r()); | ||
2938 | |||
2939 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2940 | "before stop trigger disable: " | ||
2941 | "dbgr_control0 = 0x%x dbgr_status0: 0x%x", | ||
2942 | dbgr_control0, dbgr_status0); | ||
2943 | |||
2944 | dbgr_control0 = set_field(dbgr_control0, | ||
2945 | gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(), | ||
2946 | gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f()); | ||
2947 | /* Write to broadcast registers */ | ||
2948 | gk20a_writel(g, | ||
2949 | gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0); | ||
2950 | |||
2951 | /* Read from unicast registers */ | ||
2952 | dbgr_control0 = | ||
2953 | gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); | ||
2954 | dbgr_status0 = | ||
2955 | gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_status0_r()); | ||
2956 | |||
2957 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2958 | "before run trigger: " | ||
2959 | "dbgr_control0 = 0x%x dbgr_status0: 0x%x", | ||
2960 | dbgr_control0, dbgr_status0); | ||
2961 | /* Run trigger */ | ||
2962 | dbgr_control0 |= | ||
2963 | gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(); | ||
2964 | /* Write to broadcast registers */ | ||
2965 | gk20a_writel(g, | ||
2966 | gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0); | ||
2967 | |||
2968 | /* Read from unicast registers */ | ||
2969 | dbgr_control0 = | ||
2970 | gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); | ||
2971 | dbgr_status0 = | ||
2972 | gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_status0_r()); | ||
2973 | /* run trigger is not sticky bit. SM clears it immediately */ | ||
2974 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2975 | "after run trigger: " | ||
2976 | "dbgr_control0 = 0x%x dbgr_status0: 0x%x", | ||
2977 | dbgr_control0, dbgr_status0); | ||
2978 | } | ||
2979 | |||
2915 | void gv11b_init_gr(struct gpu_ops *gops) | 2980 | void gv11b_init_gr(struct gpu_ops *gops) |
2916 | { | 2981 | { |
2917 | gp10b_init_gr(gops); | 2982 | gp10b_init_gr(gops); |
@@ -2984,4 +3049,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2984 | gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; | 3049 | gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; |
2985 | gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; | 3050 | gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; |
2986 | gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; | 3051 | gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; |
3052 | gops->gr.resume_all_sms = gv11b_gr_resume_all_sms; | ||
2987 | } | 3053 | } |