diff options
author | Sunny He <suhe@nvidia.com> | 2017-08-17 19:10:42 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-24 12:34:43 -0400 |
commit | 866165749a0b7b2e6b219bb26bffd69d790d97c5 (patch) | |
tree | 912f2df921d7a8964947efa9be6bec25cf0445d7 | |
parent | bcf556b640a3680522b03042574081abe0e17fef (diff) |
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
gr sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1542988
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 149 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 259 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 140 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 153 |
4 files changed, 516 insertions, 185 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e3c2d1cb..4f21e433 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include "gk20a/fb_gk20a.h" | 33 | #include "gk20a/fb_gk20a.h" |
34 | #include "gk20a/mm_gk20a.h" | 34 | #include "gk20a/mm_gk20a.h" |
35 | #include "gk20a/pmu_gk20a.h" | 35 | #include "gk20a/pmu_gk20a.h" |
36 | #include "gk20a/gr_gk20a.h" | ||
36 | 37 | ||
37 | #include "gm20b/ltc_gm20b.h" | 38 | #include "gm20b/ltc_gm20b.h" |
38 | #include "gm20b/gr_gm20b.h" | 39 | #include "gm20b/gr_gm20b.h" |
@@ -43,6 +44,7 @@ | |||
43 | #include "gm20b/acr_gm20b.h" | 44 | #include "gm20b/acr_gm20b.h" |
44 | 45 | ||
45 | #include "gp10b/fb_gp10b.h" | 46 | #include "gp10b/fb_gp10b.h" |
47 | #include "gp10b/gr_gp10b.h" | ||
46 | 48 | ||
47 | #include "gp106/clk_gp106.h" | 49 | #include "gp106/clk_gp106.h" |
48 | #include "gp106/clk_arb_gp106.h" | 50 | #include "gp106/clk_arb_gp106.h" |
@@ -215,6 +217,150 @@ static const struct gpu_ops gv100_ops = { | |||
215 | .isr_nonstall = gp10b_ce_nonstall_isr, | 217 | .isr_nonstall = gp10b_ce_nonstall_isr, |
216 | .get_num_pce = gv11b_ce_get_num_pce, | 218 | .get_num_pce = gv11b_ce_get_num_pce, |
217 | }, | 219 | }, |
220 | .gr = { | ||
221 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | ||
222 | .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, | ||
223 | .cb_size_default = gr_gv11b_cb_size_default, | ||
224 | .calc_global_ctx_buffer_size = | ||
225 | gr_gv11b_calc_global_ctx_buffer_size, | ||
226 | .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, | ||
227 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
228 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
229 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
230 | .handle_sw_method = gr_gv11b_handle_sw_method, | ||
231 | .set_alpha_circular_buffer_size = | ||
232 | gr_gv11b_set_alpha_circular_buffer_size, | ||
233 | .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, | ||
234 | .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, | ||
235 | .is_valid_class = gr_gv11b_is_valid_class, | ||
236 | .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, | ||
237 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | ||
238 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | ||
239 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | ||
240 | .init_fs_state = gr_gv11b_init_fs_state, | ||
241 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | ||
242 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
243 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, | ||
244 | .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, | ||
245 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | ||
246 | .free_channel_ctx = gk20a_free_channel_ctx, | ||
247 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | ||
248 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | ||
249 | .get_zcull_info = gr_gk20a_get_zcull_info, | ||
250 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
251 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
252 | .detect_sm_arch = gr_gv11b_detect_sm_arch, | ||
253 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
254 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
255 | .zbc_set_table = gk20a_gr_zbc_set_table, | ||
256 | .zbc_query_table = gr_gk20a_query_zbc, | ||
257 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
258 | .add_zbc = gr_gk20a_add_zbc, | ||
259 | .pagepool_default_size = gr_gv11b_pagepool_default_size, | ||
260 | .init_ctx_state = gr_gp10b_init_ctx_state, | ||
261 | .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, | ||
262 | .free_gr_ctx = gr_gp10b_free_gr_ctx, | ||
263 | .update_ctxsw_preemption_mode = | ||
264 | gr_gp10b_update_ctxsw_preemption_mode, | ||
265 | .dump_gr_regs = gr_gv11b_dump_gr_status_regs, | ||
266 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
267 | .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, | ||
268 | .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, | ||
269 | .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, | ||
270 | .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, | ||
271 | .get_max_fbps_count = gr_gm20b_get_max_fbps_count, | ||
272 | .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, | ||
273 | .wait_empty = gr_gv11b_wait_empty, | ||
274 | .init_cyclestats = gr_gv11b_init_cyclestats, | ||
275 | .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, | ||
276 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
277 | .bpt_reg_info = gv11b_gr_bpt_reg_info, | ||
278 | .get_access_map = gr_gv11b_get_access_map, | ||
279 | .handle_fecs_error = gr_gv11b_handle_fecs_error, | ||
280 | .handle_sm_exception = gr_gk20a_handle_sm_exception, | ||
281 | .handle_tex_exception = gr_gv11b_handle_tex_exception, | ||
282 | .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, | ||
283 | .enable_exceptions = gr_gv11b_enable_exceptions, | ||
284 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
285 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | ||
286 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | ||
287 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | ||
288 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | ||
289 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | ||
290 | .suspend_contexts = gr_gp10b_suspend_contexts, | ||
291 | .resume_contexts = gr_gk20a_resume_contexts, | ||
292 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
293 | .fuse_override = gp10b_gr_fuse_override, | ||
294 | .init_sm_id_table = gr_gv11b_init_sm_id_table, | ||
295 | .load_smid_config = gr_gv11b_load_smid_config, | ||
296 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | ||
297 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
298 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
299 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
300 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
301 | .setup_rop_mapping = gr_gv11b_setup_rop_mapping, | ||
302 | .program_zcull_mapping = gr_gv11b_program_zcull_mapping, | ||
303 | .commit_global_timeslice = gr_gv11b_commit_global_timeslice, | ||
304 | .commit_inst = gr_gv11b_commit_inst, | ||
305 | .write_zcull_ptr = gr_gv11b_write_zcull_ptr, | ||
306 | .write_pm_ptr = gr_gv11b_write_pm_ptr, | ||
307 | .init_elcg_mode = gr_gv11b_init_elcg_mode, | ||
308 | .load_tpc_mask = gr_gv11b_load_tpc_mask, | ||
309 | .inval_icache = gr_gk20a_inval_icache, | ||
310 | .trigger_suspend = gv11b_gr_sm_trigger_suspend, | ||
311 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
312 | .resume_from_pause = gv11b_gr_resume_from_pause, | ||
313 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
314 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
315 | .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, | ||
316 | .sm_debugger_attached = gv11b_gr_sm_debugger_attached, | ||
317 | .suspend_single_sm = gv11b_gr_suspend_single_sm, | ||
318 | .suspend_all_sms = gv11b_gr_suspend_all_sms, | ||
319 | .resume_single_sm = gv11b_gr_resume_single_sm, | ||
320 | .resume_all_sms = gv11b_gr_resume_all_sms, | ||
321 | .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, | ||
322 | .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, | ||
323 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
324 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
325 | .lock_down_sm = gv11b_gr_lock_down_sm, | ||
326 | .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, | ||
327 | .clear_sm_hww = gv11b_gr_clear_sm_hww, | ||
328 | .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, | ||
329 | .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, | ||
330 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
331 | .set_boosted_ctx = gr_gp10b_set_boosted_ctx, | ||
332 | .set_preemption_mode = gr_gp10b_set_preemption_mode, | ||
333 | .set_czf_bypass = NULL, | ||
334 | .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, | ||
335 | .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, | ||
336 | .init_preemption_state = NULL, | ||
337 | .update_boosted_ctx = gr_gp10b_update_boosted_ctx, | ||
338 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
339 | .create_gr_sysfs = gr_gv11b_create_sysfs, | ||
340 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, | ||
341 | .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, | ||
342 | .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, | ||
343 | .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, | ||
344 | .zbc_s_query_table = gr_gv11b_zbc_s_query_table, | ||
345 | .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, | ||
346 | .restore_context_header = gv11b_restore_context_header, | ||
347 | .handle_gpc_gpcmmu_exception = | ||
348 | gr_gv11b_handle_gpc_gpcmmu_exception, | ||
349 | .add_zbc_type_s = gr_gv11b_add_zbc_type_s, | ||
350 | .get_egpc_base = gv11b_gr_get_egpc_base, | ||
351 | .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, | ||
352 | .handle_gpc_gpccs_exception = | ||
353 | gr_gv11b_handle_gpc_gpccs_exception, | ||
354 | .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, | ||
355 | .access_smpc_reg = gv11b_gr_access_smpc_reg, | ||
356 | .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, | ||
357 | .add_zbc_s = gr_gv11b_add_zbc_stencil, | ||
358 | .handle_gcc_exception = gr_gv11b_handle_gcc_exception, | ||
359 | .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, | ||
360 | .handle_tpc_sm_ecc_exception = | ||
361 | gr_gv11b_handle_tpc_sm_ecc_exception, | ||
362 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | ||
363 | }, | ||
218 | .fb = { | 364 | .fb = { |
219 | .reset = gv100_fb_reset, | 365 | .reset = gv100_fb_reset, |
220 | .init_hw = gk20a_fb_init_hw, | 366 | .init_hw = gk20a_fb_init_hw, |
@@ -483,6 +629,7 @@ int gv100_init_hal(struct gk20a *g) | |||
483 | 629 | ||
484 | gops->ltc = gv100_ops.ltc; | 630 | gops->ltc = gv100_ops.ltc; |
485 | gops->ce2 = gv100_ops.ce2; | 631 | gops->ce2 = gv100_ops.ce2; |
632 | gops->gr = gv100_ops.gr; | ||
486 | gops->fb = gv100_ops.fb; | 633 | gops->fb = gv100_ops.fb; |
487 | gops->clock_gating = gv100_ops.clock_gating; | 634 | gops->clock_gating = gv100_ops.clock_gating; |
488 | gops->fifo = gv100_ops.fifo; | 635 | gops->fifo = gv100_ops.fifo; |
@@ -525,8 +672,6 @@ int gv100_init_hal(struct gk20a *g) | |||
525 | g->pmu_lsf_pmu_wpr_init_done = 0; | 672 | g->pmu_lsf_pmu_wpr_init_done = 0; |
526 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 673 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
527 | 674 | ||
528 | gv11b_init_gr(g); | ||
529 | |||
530 | gv11b_init_uncompressed_kind_map(); | 675 | gv11b_init_uncompressed_kind_map(); |
531 | gv11b_init_kind_attr(); | 676 | gv11b_init_kind_attr(); |
532 | 677 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 2b0e8be7..078272d1 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -51,7 +51,7 @@ | |||
51 | #include <nvgpu/hw/gv11b/hw_therm_gv11b.h> | 51 | #include <nvgpu/hw/gv11b/hw_therm_gv11b.h> |
52 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> | 52 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> |
53 | 53 | ||
54 | static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) | 54 | bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) |
55 | { | 55 | { |
56 | bool valid = false; | 56 | bool valid = false; |
57 | 57 | ||
@@ -80,7 +80,7 @@ static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) | |||
80 | return valid; | 80 | return valid; |
81 | } | 81 | } |
82 | 82 | ||
83 | static bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) | 83 | bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) |
84 | { | 84 | { |
85 | bool valid = false; | 85 | bool valid = false; |
86 | 86 | ||
@@ -97,7 +97,7 @@ static bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) | |||
97 | return valid; | 97 | return valid; |
98 | } | 98 | } |
99 | 99 | ||
100 | static bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) | 100 | bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) |
101 | { | 101 | { |
102 | bool valid = false; | 102 | bool valid = false; |
103 | 103 | ||
@@ -299,7 +299,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
299 | 299 | ||
300 | } | 300 | } |
301 | 301 | ||
302 | static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) | 302 | void gr_gv11b_enable_hww_exceptions(struct gk20a *g) |
303 | { | 303 | { |
304 | /* enable exceptions */ | 304 | /* enable exceptions */ |
305 | gk20a_writel(g, gr_fe_hww_esr_r(), | 305 | gk20a_writel(g, gr_fe_hww_esr_r(), |
@@ -310,7 +310,7 @@ static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) | |||
310 | gr_memfmt_hww_esr_reset_active_f()); | 310 | gr_memfmt_hww_esr_reset_active_f()); |
311 | } | 311 | } |
312 | 312 | ||
313 | static void gr_gv11b_enable_exceptions(struct gk20a *g) | 313 | void gr_gv11b_enable_exceptions(struct gk20a *g) |
314 | { | 314 | { |
315 | struct gr_gk20a *gr = &g->gr; | 315 | struct gr_gk20a *gr = &g->gr; |
316 | u32 reg_val; | 316 | u32 reg_val; |
@@ -581,7 +581,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
581 | 581 | ||
582 | } | 582 | } |
583 | 583 | ||
584 | static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, | 584 | int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, |
585 | u32 gpc, u32 tpc, | 585 | u32 gpc, u32 tpc, |
586 | bool *post_event, struct channel_gk20a *fault_ch, | 586 | bool *post_event, struct channel_gk20a *fault_ch, |
587 | u32 *hww_global_esr) | 587 | u32 *hww_global_esr) |
@@ -606,7 +606,7 @@ static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, | |||
606 | return ret; | 606 | return ret; |
607 | } | 607 | } |
608 | 608 | ||
609 | static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | 609 | int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, |
610 | bool *post_event, struct channel_gk20a *fault_ch, | 610 | bool *post_event, struct channel_gk20a *fault_ch, |
611 | u32 *hww_global_esr) | 611 | u32 *hww_global_esr) |
612 | { | 612 | { |
@@ -852,7 +852,7 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | |||
852 | return ret; | 852 | return ret; |
853 | } | 853 | } |
854 | 854 | ||
855 | static int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, | 855 | int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, |
856 | u32 gpc_exception) | 856 | u32 gpc_exception) |
857 | { | 857 | { |
858 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m()) | 858 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m()) |
@@ -861,7 +861,7 @@ static int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, | |||
861 | return 0; | 861 | return 0; |
862 | } | 862 | } |
863 | 863 | ||
864 | static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, | 864 | int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, |
865 | u32 gpc_exception) | 865 | u32 gpc_exception) |
866 | { | 866 | { |
867 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) | 867 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) |
@@ -871,7 +871,7 @@ static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, | |||
871 | return 0; | 871 | return 0; |
872 | } | 872 | } |
873 | 873 | ||
874 | static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) | 874 | void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) |
875 | { | 875 | { |
876 | struct gr_gk20a *gr = &g->gr; | 876 | struct gr_gk20a *gr = &g->gr; |
877 | u32 tpc_mask; | 877 | u32 tpc_mask; |
@@ -889,13 +889,13 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) | |||
889 | gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1))); | 889 | gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1))); |
890 | } | 890 | } |
891 | 891 | ||
892 | static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | 892 | int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, |
893 | bool *post_event) | 893 | bool *post_event) |
894 | { | 894 | { |
895 | return 0; | 895 | return 0; |
896 | } | 896 | } |
897 | 897 | ||
898 | static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, | 898 | int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, |
899 | struct zbc_query_params *query_params) | 899 | struct zbc_query_params *query_params) |
900 | { | 900 | { |
901 | u32 index = query_params->index_size; | 901 | u32 index = query_params->index_size; |
@@ -911,7 +911,7 @@ static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, | |||
911 | return 0; | 911 | return 0; |
912 | } | 912 | } |
913 | 913 | ||
914 | static bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, | 914 | bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, |
915 | struct zbc_entry *zbc_val, int *ret_val) | 915 | struct zbc_entry *zbc_val, int *ret_val) |
916 | { | 916 | { |
917 | struct zbc_s_table *s_tbl; | 917 | struct zbc_s_table *s_tbl; |
@@ -950,7 +950,7 @@ static bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, | |||
950 | return added; | 950 | return added; |
951 | } | 951 | } |
952 | 952 | ||
953 | static int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, | 953 | int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, |
954 | struct zbc_entry *stencil_val, u32 index) | 954 | struct zbc_entry *stencil_val, u32 index) |
955 | { | 955 | { |
956 | u32 zbc_s; | 956 | u32 zbc_s; |
@@ -974,7 +974,7 @@ static int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, | |||
974 | return 0; | 974 | return 0; |
975 | } | 975 | } |
976 | 976 | ||
977 | static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, | 977 | int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, |
978 | struct gr_gk20a *gr) | 978 | struct gr_gk20a *gr) |
979 | { | 979 | { |
980 | struct zbc_entry zbc_val; | 980 | struct zbc_entry zbc_val; |
@@ -1005,7 +1005,7 @@ static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, | |||
1005 | return 0; | 1005 | return 0; |
1006 | } | 1006 | } |
1007 | 1007 | ||
1008 | static int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) | 1008 | int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) |
1009 | { | 1009 | { |
1010 | int ret; | 1010 | int ret; |
1011 | u32 i; | 1011 | u32 i; |
@@ -1025,12 +1025,12 @@ static int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) | |||
1025 | return 0; | 1025 | return 0; |
1026 | } | 1026 | } |
1027 | 1027 | ||
1028 | static u32 gr_gv11b_pagepool_default_size(struct gk20a *g) | 1028 | u32 gr_gv11b_pagepool_default_size(struct gk20a *g) |
1029 | { | 1029 | { |
1030 | return gr_scc_pagepool_total_pages_hwmax_value_v(); | 1030 | return gr_scc_pagepool_total_pages_hwmax_value_v(); |
1031 | } | 1031 | } |
1032 | 1032 | ||
1033 | static int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) | 1033 | int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) |
1034 | { | 1034 | { |
1035 | struct gr_gk20a *gr = &g->gr; | 1035 | struct gr_gk20a *gr = &g->gr; |
1036 | int size; | 1036 | int size; |
@@ -1138,7 +1138,7 @@ static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) | |||
1138 | } | 1138 | } |
1139 | } | 1139 | } |
1140 | 1140 | ||
1141 | static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | 1141 | int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, |
1142 | u32 class_num, u32 offset, u32 data) | 1142 | u32 class_num, u32 offset, u32 data) |
1143 | { | 1143 | { |
1144 | gk20a_dbg_fn(""); | 1144 | gk20a_dbg_fn(""); |
@@ -1192,7 +1192,7 @@ fail: | |||
1192 | return -EINVAL; | 1192 | return -EINVAL; |
1193 | } | 1193 | } |
1194 | 1194 | ||
1195 | static void gr_gv11b_bundle_cb_defaults(struct gk20a *g) | 1195 | void gr_gv11b_bundle_cb_defaults(struct gk20a *g) |
1196 | { | 1196 | { |
1197 | struct gr_gk20a *gr = &g->gr; | 1197 | struct gr_gk20a *gr = &g->gr; |
1198 | 1198 | ||
@@ -1204,7 +1204,7 @@ static void gr_gv11b_bundle_cb_defaults(struct gk20a *g) | |||
1204 | gr_pd_ab_dist_cfg2_token_limit_init_v(); | 1204 | gr_pd_ab_dist_cfg2_token_limit_init_v(); |
1205 | } | 1205 | } |
1206 | 1206 | ||
1207 | static void gr_gv11b_cb_size_default(struct gk20a *g) | 1207 | void gr_gv11b_cb_size_default(struct gk20a *g) |
1208 | { | 1208 | { |
1209 | struct gr_gk20a *gr = &g->gr; | 1209 | struct gr_gk20a *gr = &g->gr; |
1210 | 1210 | ||
@@ -1215,7 +1215,7 @@ static void gr_gv11b_cb_size_default(struct gk20a *g) | |||
1215 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); | 1215 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); |
1216 | } | 1216 | } |
1217 | 1217 | ||
1218 | static void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) | 1218 | void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) |
1219 | { | 1219 | { |
1220 | struct gr_gk20a *gr = &g->gr; | 1220 | struct gr_gk20a *gr = &g->gr; |
1221 | u32 gpc_index, ppc_index, stride, val; | 1221 | u32 gpc_index, ppc_index, stride, val; |
@@ -1261,7 +1261,7 @@ static void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) | |||
1261 | } | 1261 | } |
1262 | } | 1262 | } |
1263 | 1263 | ||
1264 | static void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) | 1264 | void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) |
1265 | { | 1265 | { |
1266 | struct gr_gk20a *gr = &g->gr; | 1266 | struct gr_gk20a *gr = &g->gr; |
1267 | u32 gpc_index, ppc_index, stride, val; | 1267 | u32 gpc_index, ppc_index, stride, val; |
@@ -1442,7 +1442,7 @@ static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g, | |||
1442 | return 0; | 1442 | return 0; |
1443 | } | 1443 | } |
1444 | 1444 | ||
1445 | static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | 1445 | int gr_gv11b_dump_gr_status_regs(struct gk20a *g, |
1446 | struct gk20a_debug_output *o) | 1446 | struct gk20a_debug_output *o) |
1447 | { | 1447 | { |
1448 | struct gr_gk20a *gr = &g->gr; | 1448 | struct gr_gk20a *gr = &g->gr; |
@@ -1595,7 +1595,7 @@ static bool gr_activity_empty_or_preempted(u32 val) | |||
1595 | return true; | 1595 | return true; |
1596 | } | 1596 | } |
1597 | 1597 | ||
1598 | static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, | 1598 | int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, |
1599 | u32 expect_delay) | 1599 | u32 expect_delay) |
1600 | { | 1600 | { |
1601 | u32 delay = expect_delay; | 1601 | u32 delay = expect_delay; |
@@ -1647,7 +1647,7 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, | |||
1647 | return -EAGAIN; | 1647 | return -EAGAIN; |
1648 | } | 1648 | } |
1649 | 1649 | ||
1650 | static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | 1650 | void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, |
1651 | struct channel_ctx_gk20a *ch_ctx, | 1651 | struct channel_ctx_gk20a *ch_ctx, |
1652 | u64 addr, bool patch) | 1652 | u64 addr, bool patch) |
1653 | { | 1653 | { |
@@ -1676,7 +1676,7 @@ static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | |||
1676 | } | 1676 | } |
1677 | 1677 | ||
1678 | 1678 | ||
1679 | static void gr_gv11b_init_cyclestats(struct gk20a *g) | 1679 | void gr_gv11b_init_cyclestats(struct gk20a *g) |
1680 | { | 1680 | { |
1681 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 1681 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
1682 | g->gpu_characteristics.flags |= | 1682 | g->gpu_characteristics.flags |= |
@@ -1688,7 +1688,7 @@ static void gr_gv11b_init_cyclestats(struct gk20a *g) | |||
1688 | #endif | 1688 | #endif |
1689 | } | 1689 | } |
1690 | 1690 | ||
1691 | static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1691 | void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1692 | { | 1692 | { |
1693 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | 1693 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) |
1694 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); | 1694 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); |
@@ -1706,7 +1706,7 @@ static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
1706 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1706 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); |
1707 | } | 1707 | } |
1708 | 1708 | ||
1709 | static void gr_gv11b_get_access_map(struct gk20a *g, | 1709 | void gr_gv11b_get_access_map(struct gk20a *g, |
1710 | u32 **whitelist, int *num_entries) | 1710 | u32 **whitelist, int *num_entries) |
1711 | { | 1711 | { |
1712 | static u32 wl_addr_gv11b[] = { | 1712 | static u32 wl_addr_gv11b[] = { |
@@ -1751,7 +1751,7 @@ static void gr_gv11b_get_access_map(struct gk20a *g, | |||
1751 | * | 1751 | * |
1752 | * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing | 1752 | * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing |
1753 | */ | 1753 | */ |
1754 | static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | 1754 | int gr_gv11b_pre_process_sm_exception(struct gk20a *g, |
1755 | u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, | 1755 | u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, |
1756 | bool sm_debugger_attached, struct channel_gk20a *fault_ch, | 1756 | bool sm_debugger_attached, struct channel_gk20a *fault_ch, |
1757 | bool *early_exit, bool *ignore_debugger) | 1757 | bool *early_exit, bool *ignore_debugger) |
@@ -1940,7 +1940,7 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) | |||
1940 | } | 1940 | } |
1941 | } | 1941 | } |
1942 | 1942 | ||
1943 | static int gr_gv11b_handle_fecs_error(struct gk20a *g, | 1943 | int gr_gv11b_handle_fecs_error(struct gk20a *g, |
1944 | struct channel_gk20a *__ch, | 1944 | struct channel_gk20a *__ch, |
1945 | struct gr_gk20a_isr_data *isr_data) | 1945 | struct gr_gk20a_isr_data *isr_data) |
1946 | { | 1946 | { |
@@ -1957,7 +1957,7 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, | |||
1957 | return ret; | 1957 | return ret; |
1958 | } | 1958 | } |
1959 | 1959 | ||
1960 | static int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) | 1960 | int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) |
1961 | { | 1961 | { |
1962 | u32 map; | 1962 | u32 map; |
1963 | u32 i, j, mapregs; | 1963 | u32 i, j, mapregs; |
@@ -2034,7 +2034,7 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) | |||
2034 | } | 2034 | } |
2035 | } | 2035 | } |
2036 | 2036 | ||
2037 | static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) | 2037 | int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) |
2038 | { | 2038 | { |
2039 | struct av_list_gk20a *sw_veid_bundle_init = | 2039 | struct av_list_gk20a *sw_veid_bundle_init = |
2040 | &g->gr.ctx_vars.sw_veid_bundle_init; | 2040 | &g->gr.ctx_vars.sw_veid_bundle_init; |
@@ -2099,7 +2099,7 @@ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, | |||
2099 | } | 2099 | } |
2100 | } | 2100 | } |
2101 | 2101 | ||
2102 | static void gr_gv11b_detect_sm_arch(struct gk20a *g) | 2102 | void gr_gv11b_detect_sm_arch(struct gk20a *g) |
2103 | { | 2103 | { |
2104 | u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); | 2104 | u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); |
2105 | 2105 | ||
@@ -2111,7 +2111,7 @@ static void gr_gv11b_detect_sm_arch(struct gk20a *g) | |||
2111 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); | 2111 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); |
2112 | } | 2112 | } |
2113 | 2113 | ||
2114 | static void gr_gv11b_init_sm_id_table(struct gk20a *g) | 2114 | void gr_gv11b_init_sm_id_table(struct gk20a *g) |
2115 | { | 2115 | { |
2116 | u32 gpc, tpc, sm; | 2116 | u32 gpc, tpc, sm; |
2117 | u32 sm_id = 0; | 2117 | u32 sm_id = 0; |
@@ -2138,7 +2138,7 @@ static void gr_gv11b_init_sm_id_table(struct gk20a *g) | |||
2138 | nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); | 2138 | nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); |
2139 | } | 2139 | } |
2140 | 2140 | ||
2141 | static void gr_gv11b_program_sm_id_numbering(struct gk20a *g, | 2141 | void gr_gv11b_program_sm_id_numbering(struct gk20a *g, |
2142 | u32 gpc, u32 tpc, u32 smid) | 2142 | u32 gpc, u32 tpc, u32 smid) |
2143 | { | 2143 | { |
2144 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 2144 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
@@ -2156,7 +2156,7 @@ static void gr_gv11b_program_sm_id_numbering(struct gk20a *g, | |||
2156 | gr_gpc0_tpc0_pe_cfg_smid_value_f(global_tpc_index)); | 2156 | gr_gpc0_tpc0_pe_cfg_smid_value_f(global_tpc_index)); |
2157 | } | 2157 | } |
2158 | 2158 | ||
2159 | static int gr_gv11b_load_smid_config(struct gk20a *g) | 2159 | int gr_gv11b_load_smid_config(struct gk20a *g) |
2160 | { | 2160 | { |
2161 | u32 *tpc_sm_id; | 2161 | u32 *tpc_sm_id; |
2162 | u32 i, j; | 2162 | u32 i, j; |
@@ -2204,7 +2204,7 @@ static int gr_gv11b_load_smid_config(struct gk20a *g) | |||
2204 | return 0; | 2204 | return 0; |
2205 | } | 2205 | } |
2206 | 2206 | ||
2207 | static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | 2207 | int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) |
2208 | { | 2208 | { |
2209 | u32 addr_lo; | 2209 | u32 addr_lo; |
2210 | u32 addr_hi; | 2210 | u32 addr_hi; |
@@ -2239,7 +2239,7 @@ static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
2239 | 2239 | ||
2240 | 2240 | ||
2241 | 2241 | ||
2242 | static int gr_gv11b_commit_global_timeslice(struct gk20a *g, | 2242 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, |
2243 | struct channel_gk20a *c, bool patch) | 2243 | struct channel_gk20a *c, bool patch) |
2244 | { | 2244 | { |
2245 | struct channel_ctx_gk20a *ch_ctx = NULL; | 2245 | struct channel_ctx_gk20a *ch_ctx = NULL; |
@@ -2292,7 +2292,7 @@ static int gr_gv11b_commit_global_timeslice(struct gk20a *g, | |||
2292 | return 0; | 2292 | return 0; |
2293 | } | 2293 | } |
2294 | 2294 | ||
2295 | static void gv11b_restore_context_header(struct gk20a *g, | 2295 | void gv11b_restore_context_header(struct gk20a *g, |
2296 | struct nvgpu_mem *ctxheader) | 2296 | struct nvgpu_mem *ctxheader) |
2297 | { | 2297 | { |
2298 | u32 va_lo, va_hi; | 2298 | u32 va_lo, va_hi; |
@@ -2314,7 +2314,7 @@ static void gv11b_restore_context_header(struct gk20a *g, | |||
2314 | nvgpu_mem_wr(g, ctxheader, | 2314 | nvgpu_mem_wr(g, ctxheader, |
2315 | ctxsw_prog_main_image_num_save_ops_o(), 0); | 2315 | ctxsw_prog_main_image_num_save_ops_o(), 0); |
2316 | } | 2316 | } |
2317 | static void gr_gv11b_write_zcull_ptr(struct gk20a *g, | 2317 | void gr_gv11b_write_zcull_ptr(struct gk20a *g, |
2318 | struct nvgpu_mem *mem, u64 gpu_va) | 2318 | struct nvgpu_mem *mem, u64 gpu_va) |
2319 | { | 2319 | { |
2320 | u32 va_lo, va_hi; | 2320 | u32 va_lo, va_hi; |
@@ -2329,7 +2329,7 @@ static void gr_gv11b_write_zcull_ptr(struct gk20a *g, | |||
2329 | } | 2329 | } |
2330 | 2330 | ||
2331 | 2331 | ||
2332 | static void gr_gv11b_write_pm_ptr(struct gk20a *g, | 2332 | void gr_gv11b_write_pm_ptr(struct gk20a *g, |
2333 | struct nvgpu_mem *mem, u64 gpu_va) | 2333 | struct nvgpu_mem *mem, u64 gpu_va) |
2334 | { | 2334 | { |
2335 | u32 va_lo, va_hi; | 2335 | u32 va_lo, va_hi; |
@@ -2343,7 +2343,7 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g, | |||
2343 | ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); | 2343 | ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); |
2344 | } | 2344 | } |
2345 | 2345 | ||
2346 | static void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | 2346 | void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) |
2347 | { | 2347 | { |
2348 | u32 gate_ctrl; | 2348 | u32 gate_ctrl; |
2349 | 2349 | ||
@@ -2375,7 +2375,7 @@ static void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) | |||
2375 | gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); | 2375 | gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); |
2376 | } | 2376 | } |
2377 | 2377 | ||
2378 | static void gr_gv11b_load_tpc_mask(struct gk20a *g) | 2378 | void gr_gv11b_load_tpc_mask(struct gk20a *g) |
2379 | { | 2379 | { |
2380 | u32 pes_tpc_mask = 0, fuse_tpc_mask; | 2380 | u32 pes_tpc_mask = 0, fuse_tpc_mask; |
2381 | u32 gpc, pes, val; | 2381 | u32 gpc, pes, val; |
@@ -2405,7 +2405,7 @@ static void gr_gv11b_load_tpc_mask(struct gk20a *g) | |||
2405 | 2405 | ||
2406 | } | 2406 | } |
2407 | 2407 | ||
2408 | static void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, | 2408 | void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, |
2409 | struct nvgpu_mem *mem, u64 gpu_va) | 2409 | struct nvgpu_mem *mem, u64 gpu_va) |
2410 | { | 2410 | { |
2411 | u32 addr_lo, addr_hi; | 2411 | u32 addr_lo, addr_hi; |
@@ -2426,7 +2426,7 @@ static void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, | |||
2426 | 2426 | ||
2427 | } | 2427 | } |
2428 | 2428 | ||
2429 | static int gr_gv11b_init_fs_state(struct gk20a *g) | 2429 | int gr_gv11b_init_fs_state(struct gk20a *g) |
2430 | { | 2430 | { |
2431 | u32 data; | 2431 | u32 data; |
2432 | 2432 | ||
@@ -2451,7 +2451,7 @@ static int gr_gv11b_init_fs_state(struct gk20a *g) | |||
2451 | return gr_gm20b_init_fs_state(g); | 2451 | return gr_gm20b_init_fs_state(g); |
2452 | } | 2452 | } |
2453 | 2453 | ||
2454 | static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | 2454 | void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, |
2455 | u32 *esr_sm_sel) | 2455 | u32 *esr_sm_sel) |
2456 | { | 2456 | { |
2457 | u32 reg_val; | 2457 | u32 reg_val; |
@@ -2469,7 +2469,7 @@ static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | |||
2469 | "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); | 2469 | "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); |
2470 | } | 2470 | } |
2471 | 2471 | ||
2472 | static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) | 2472 | int gv11b_gr_sm_trigger_suspend(struct gk20a *g) |
2473 | { | 2473 | { |
2474 | u32 dbgr_control0; | 2474 | u32 dbgr_control0; |
2475 | 2475 | ||
@@ -2491,7 +2491,7 @@ static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) | |||
2491 | return 0; | 2491 | return 0; |
2492 | } | 2492 | } |
2493 | 2493 | ||
2494 | static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | 2494 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) |
2495 | { | 2495 | { |
2496 | /* Check if we have at least one valid warp | 2496 | /* Check if we have at least one valid warp |
2497 | * get paused state on maxwell | 2497 | * get paused state on maxwell |
@@ -2559,7 +2559,7 @@ static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | |||
2559 | } | 2559 | } |
2560 | } | 2560 | } |
2561 | 2561 | ||
2562 | static int gv11b_gr_update_sm_error_state(struct gk20a *g, | 2562 | int gv11b_gr_update_sm_error_state(struct gk20a *g, |
2563 | struct channel_gk20a *ch, u32 sm_id, | 2563 | struct channel_gk20a *ch, u32 sm_id, |
2564 | struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) | 2564 | struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) |
2565 | { | 2565 | { |
@@ -2638,7 +2638,7 @@ fail: | |||
2638 | return err; | 2638 | return err; |
2639 | } | 2639 | } |
2640 | 2640 | ||
2641 | static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | 2641 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, |
2642 | struct channel_gk20a *ch, u64 sms, bool enable) | 2642 | struct channel_gk20a *ch, u64 sms, bool enable) |
2643 | { | 2643 | { |
2644 | struct nvgpu_dbg_gpu_reg_op *ops; | 2644 | struct nvgpu_dbg_gpu_reg_op *ops; |
@@ -2697,7 +2697,7 @@ static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | |||
2697 | return err; | 2697 | return err; |
2698 | } | 2698 | } |
2699 | 2699 | ||
2700 | static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | 2700 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) |
2701 | { | 2701 | { |
2702 | int sm_id; | 2702 | int sm_id; |
2703 | struct gr_gk20a *gr = &g->gr; | 2703 | struct gr_gk20a *gr = &g->gr; |
@@ -2737,7 +2737,7 @@ static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | |||
2737 | return 0; | 2737 | return 0; |
2738 | } | 2738 | } |
2739 | 2739 | ||
2740 | static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) | 2740 | void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) |
2741 | { | 2741 | { |
2742 | 2742 | ||
2743 | /* clear hww */ | 2743 | /* clear hww */ |
@@ -2767,7 +2767,7 @@ static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) | |||
2767 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()); | 2767 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()); |
2768 | } | 2768 | } |
2769 | 2769 | ||
2770 | static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) | 2770 | bool gv11b_gr_sm_debugger_attached(struct gk20a *g) |
2771 | { | 2771 | { |
2772 | u32 debugger_mode; | 2772 | u32 debugger_mode; |
2773 | u32 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); | 2773 | u32 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); |
@@ -2787,7 +2787,7 @@ static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) | |||
2787 | return false; | 2787 | return false; |
2788 | } | 2788 | } |
2789 | 2789 | ||
2790 | static void gv11b_gr_suspend_single_sm(struct gk20a *g, | 2790 | void gv11b_gr_suspend_single_sm(struct gk20a *g, |
2791 | u32 gpc, u32 tpc, u32 sm, | 2791 | u32 gpc, u32 tpc, u32 sm, |
2792 | u32 global_esr_mask, bool check_errors) | 2792 | u32 global_esr_mask, bool check_errors) |
2793 | { | 2793 | { |
@@ -2823,7 +2823,7 @@ static void gv11b_gr_suspend_single_sm(struct gk20a *g, | |||
2823 | } | 2823 | } |
2824 | } | 2824 | } |
2825 | 2825 | ||
2826 | static void gv11b_gr_suspend_all_sms(struct gk20a *g, | 2826 | void gv11b_gr_suspend_all_sms(struct gk20a *g, |
2827 | u32 global_esr_mask, bool check_errors) | 2827 | u32 global_esr_mask, bool check_errors) |
2828 | { | 2828 | { |
2829 | struct gr_gk20a *gr = &g->gr; | 2829 | struct gr_gk20a *gr = &g->gr; |
@@ -2868,7 +2868,7 @@ static void gv11b_gr_suspend_all_sms(struct gk20a *g, | |||
2868 | } | 2868 | } |
2869 | } | 2869 | } |
2870 | 2870 | ||
2871 | static void gv11b_gr_resume_single_sm(struct gk20a *g, | 2871 | void gv11b_gr_resume_single_sm(struct gk20a *g, |
2872 | u32 gpc, u32 tpc, u32 sm) | 2872 | u32 gpc, u32 tpc, u32 sm) |
2873 | { | 2873 | { |
2874 | u32 dbgr_control0, dbgr_status0; | 2874 | u32 dbgr_control0, dbgr_status0; |
@@ -2936,7 +2936,7 @@ static void gv11b_gr_resume_single_sm(struct gk20a *g, | |||
2936 | 2936 | ||
2937 | } | 2937 | } |
2938 | 2938 | ||
2939 | static void gv11b_gr_resume_all_sms(struct gk20a *g) | 2939 | void gv11b_gr_resume_all_sms(struct gk20a *g) |
2940 | { | 2940 | { |
2941 | u32 dbgr_control0, dbgr_status0; | 2941 | u32 dbgr_control0, dbgr_status0; |
2942 | /* | 2942 | /* |
@@ -3001,7 +3001,7 @@ static void gv11b_gr_resume_all_sms(struct gk20a *g) | |||
3001 | dbgr_control0, dbgr_status0); | 3001 | dbgr_control0, dbgr_status0); |
3002 | } | 3002 | } |
3003 | 3003 | ||
3004 | static int gv11b_gr_resume_from_pause(struct gk20a *g) | 3004 | int gv11b_gr_resume_from_pause(struct gk20a *g) |
3005 | { | 3005 | { |
3006 | int err = 0; | 3006 | int err = 0; |
3007 | u32 reg_val; | 3007 | u32 reg_val; |
@@ -3020,7 +3020,7 @@ static int gv11b_gr_resume_from_pause(struct gk20a *g) | |||
3020 | return err; | 3020 | return err; |
3021 | } | 3021 | } |
3022 | 3022 | ||
3023 | static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, | 3023 | u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, |
3024 | u32 gpc, u32 tpc, u32 sm) | 3024 | u32 gpc, u32 tpc, u32 sm) |
3025 | { | 3025 | { |
3026 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + | 3026 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + |
@@ -3032,7 +3032,7 @@ static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, | |||
3032 | return hww_warp_esr; | 3032 | return hww_warp_esr; |
3033 | } | 3033 | } |
3034 | 3034 | ||
3035 | static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, | 3035 | u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, |
3036 | u32 gpc, u32 tpc, u32 sm) | 3036 | u32 gpc, u32 tpc, u32 sm) |
3037 | { | 3037 | { |
3038 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + | 3038 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + |
@@ -3045,7 +3045,7 @@ static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, | |||
3045 | return hww_global_esr; | 3045 | return hww_global_esr; |
3046 | } | 3046 | } |
3047 | 3047 | ||
3048 | static u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) | 3048 | u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) |
3049 | { | 3049 | { |
3050 | /* | 3050 | /* |
3051 | * These three interrupts don't require locking down the SM. They can | 3051 | * These three interrupts don't require locking down the SM. They can |
@@ -3104,7 +3104,7 @@ static void gv11b_gr_sm_dump_warp_bpt_pause_trap_mask_regs(struct gk20a *g, | |||
3104 | warps_paused, warps_trapped); | 3104 | warps_paused, warps_trapped); |
3105 | } | 3105 | } |
3106 | 3106 | ||
3107 | static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, | 3107 | int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, |
3108 | u32 gpc, u32 tpc, u32 sm, | 3108 | u32 gpc, u32 tpc, u32 sm, |
3109 | u32 global_esr_mask, bool check_errors) | 3109 | u32 global_esr_mask, bool check_errors) |
3110 | { | 3110 | { |
@@ -3190,7 +3190,7 @@ static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, | |||
3190 | return -ETIMEDOUT; | 3190 | return -ETIMEDOUT; |
3191 | } | 3191 | } |
3192 | 3192 | ||
3193 | static int gv11b_gr_lock_down_sm(struct gk20a *g, | 3193 | int gv11b_gr_lock_down_sm(struct gk20a *g, |
3194 | u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, | 3194 | u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, |
3195 | bool check_errors) | 3195 | bool check_errors) |
3196 | { | 3196 | { |
@@ -3212,7 +3212,7 @@ static int gv11b_gr_lock_down_sm(struct gk20a *g, | |||
3212 | check_errors); | 3212 | check_errors); |
3213 | } | 3213 | } |
3214 | 3214 | ||
3215 | static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 3215 | void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
3216 | u32 global_esr) | 3216 | u32 global_esr) |
3217 | { | 3217 | { |
3218 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + | 3218 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + |
@@ -3232,7 +3232,7 @@ static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
3232 | offset)); | 3232 | offset)); |
3233 | } | 3233 | } |
3234 | 3234 | ||
3235 | static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, | 3235 | int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, |
3236 | u32 gpc, u32 tpc, bool *post_event) | 3236 | u32 gpc, u32 tpc, bool *post_event) |
3237 | { | 3237 | { |
3238 | u32 esr; | 3238 | u32 esr; |
@@ -3263,7 +3263,7 @@ static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, | |||
3263 | static const u32 _num_ovr_perf_regs = 20; | 3263 | static const u32 _num_ovr_perf_regs = 20; |
3264 | static u32 _ovr_perf_regs[20] = { 0, }; | 3264 | static u32 _ovr_perf_regs[20] = { 0, }; |
3265 | 3265 | ||
3266 | static void gv11b_gr_init_ovr_sm_dsm_perf(void) | 3266 | void gv11b_gr_init_ovr_sm_dsm_perf(void) |
3267 | { | 3267 | { |
3268 | if (_ovr_perf_regs[0] != 0) | 3268 | if (_ovr_perf_regs[0] != 0) |
3269 | return; | 3269 | return; |
@@ -3301,7 +3301,7 @@ static const u32 _num_sm_dsm_perf_ctrl_regs = 2; | |||
3301 | static u32 *_sm_dsm_perf_regs; | 3301 | static u32 *_sm_dsm_perf_regs; |
3302 | static u32 _sm_dsm_perf_ctrl_regs[2]; | 3302 | static u32 _sm_dsm_perf_ctrl_regs[2]; |
3303 | 3303 | ||
3304 | static void gv11b_gr_init_sm_dsm_reg_info(void) | 3304 | void gv11b_gr_init_sm_dsm_reg_info(void) |
3305 | { | 3305 | { |
3306 | if (_sm_dsm_perf_ctrl_regs[0] != 0) | 3306 | if (_sm_dsm_perf_ctrl_regs[0] != 0) |
3307 | return; | 3307 | return; |
@@ -3312,7 +3312,7 @@ static void gv11b_gr_init_sm_dsm_reg_info(void) | |||
3312 | gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(); | 3312 | gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(); |
3313 | } | 3313 | } |
3314 | 3314 | ||
3315 | static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, | 3315 | void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, |
3316 | u32 *num_sm_dsm_perf_regs, | 3316 | u32 *num_sm_dsm_perf_regs, |
3317 | u32 **sm_dsm_perf_regs, | 3317 | u32 **sm_dsm_perf_regs, |
3318 | u32 *perf_register_stride) | 3318 | u32 *perf_register_stride) |
@@ -3323,7 +3323,7 @@ static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, | |||
3323 | ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); | 3323 | ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); |
3324 | } | 3324 | } |
3325 | 3325 | ||
3326 | static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | 3326 | void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, |
3327 | u32 *num_sm_dsm_perf_ctrl_regs, | 3327 | u32 *num_sm_dsm_perf_ctrl_regs, |
3328 | u32 **sm_dsm_perf_ctrl_regs, | 3328 | u32 **sm_dsm_perf_ctrl_regs, |
3329 | u32 *ctrl_register_stride) | 3329 | u32 *ctrl_register_stride) |
@@ -3334,14 +3334,14 @@ static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | |||
3334 | ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); | 3334 | ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); |
3335 | } | 3335 | } |
3336 | 3336 | ||
3337 | static void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, | 3337 | void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, |
3338 | u32 **ovr_perf_regs) | 3338 | u32 **ovr_perf_regs) |
3339 | { | 3339 | { |
3340 | *num_ovr_perf_regs = _num_ovr_perf_regs; | 3340 | *num_ovr_perf_regs = _num_ovr_perf_regs; |
3341 | *ovr_perf_regs = _ovr_perf_regs; | 3341 | *ovr_perf_regs = _ovr_perf_regs; |
3342 | } | 3342 | } |
3343 | 3343 | ||
3344 | static void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) | 3344 | void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) |
3345 | { | 3345 | { |
3346 | u32 reg_val; | 3346 | u32 reg_val; |
3347 | u32 quad_ctrl; | 3347 | u32 quad_ctrl; |
@@ -3393,7 +3393,7 @@ static bool pri_is_egpc_addr_shared(struct gk20a *g, u32 addr) | |||
3393 | (addr < egpc_shared_base + gpc_stride); | 3393 | (addr < egpc_shared_base + gpc_stride); |
3394 | } | 3394 | } |
3395 | 3395 | ||
3396 | static bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) | 3396 | bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) |
3397 | { | 3397 | { |
3398 | u32 egpc_base = g->ops.gr.get_egpc_base(g); | 3398 | u32 egpc_base = g->ops.gr.get_egpc_base(g); |
3399 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 3399 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
@@ -3404,7 +3404,7 @@ static bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) | |||
3404 | pri_is_egpc_addr_shared(g, addr); | 3404 | pri_is_egpc_addr_shared(g, addr); |
3405 | } | 3405 | } |
3406 | 3406 | ||
3407 | static bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) | 3407 | bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) |
3408 | { | 3408 | { |
3409 | u32 egpc_addr = 0; | 3409 | u32 egpc_addr = 0; |
3410 | 3410 | ||
@@ -3454,7 +3454,7 @@ static u32 pri_etpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc) | |||
3454 | addr; | 3454 | addr; |
3455 | } | 3455 | } |
3456 | 3456 | ||
3457 | static void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, | 3457 | void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, |
3458 | u32 *egpc_num, u32 *etpc_num) | 3458 | u32 *egpc_num, u32 *etpc_num) |
3459 | { | 3459 | { |
3460 | u32 egpc_addr = 0; | 3460 | u32 egpc_addr = 0; |
@@ -3467,7 +3467,7 @@ static void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, | |||
3467 | "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num); | 3467 | "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num); |
3468 | } | 3468 | } |
3469 | 3469 | ||
3470 | static int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, | 3470 | int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, |
3471 | u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) | 3471 | u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) |
3472 | { | 3472 | { |
3473 | u32 gpc_addr; | 3473 | u32 gpc_addr; |
@@ -3506,7 +3506,7 @@ static int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, | |||
3506 | return -EINVAL; | 3506 | return -EINVAL; |
3507 | } | 3507 | } |
3508 | 3508 | ||
3509 | static void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, | 3509 | void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, |
3510 | u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t) | 3510 | u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t) |
3511 | { | 3511 | { |
3512 | u32 gpc_num, tpc_num; | 3512 | u32 gpc_num, tpc_num; |
@@ -3569,12 +3569,12 @@ static void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, | |||
3569 | } | 3569 | } |
3570 | } | 3570 | } |
3571 | 3571 | ||
3572 | static u32 gv11b_gr_get_egpc_base(struct gk20a *g) | 3572 | u32 gv11b_gr_get_egpc_base(struct gk20a *g) |
3573 | { | 3573 | { |
3574 | return EGPC_PRI_BASE; | 3574 | return EGPC_PRI_BASE; |
3575 | } | 3575 | } |
3576 | 3576 | ||
3577 | static void gr_gv11b_init_gpc_mmu(struct gk20a *g) | 3577 | void gr_gv11b_init_gpc_mmu(struct gk20a *g) |
3578 | { | 3578 | { |
3579 | u32 temp; | 3579 | u32 temp; |
3580 | 3580 | ||
@@ -3606,104 +3606,3 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g) | |||
3606 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), | 3606 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), |
3607 | gk20a_readl(g, fb_mmu_debug_rd_r())); | 3607 | gk20a_readl(g, fb_mmu_debug_rd_r())); |
3608 | } | 3608 | } |
3609 | |||
3610 | void gv11b_init_gr(struct gk20a *g) | ||
3611 | { | ||
3612 | struct gpu_ops *gops = &g->ops; | ||
3613 | |||
3614 | gp10b_init_gr(g); | ||
3615 | gops->gr.init_preemption_state = NULL; | ||
3616 | gops->gr.init_fs_state = gr_gv11b_init_fs_state; | ||
3617 | gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch; | ||
3618 | gops->gr.is_valid_class = gr_gv11b_is_valid_class; | ||
3619 | gops->gr.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class; | ||
3620 | gops->gr.is_valid_compute_class = gr_gv11b_is_valid_compute_class; | ||
3621 | gops->gr.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va; | ||
3622 | gops->gr.add_zbc_s = gr_gv11b_add_zbc_stencil; | ||
3623 | gops->gr.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl; | ||
3624 | gops->gr.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl; | ||
3625 | gops->gr.zbc_s_query_table = gr_gv11b_zbc_s_query_table; | ||
3626 | gops->gr.add_zbc_type_s = gr_gv11b_add_zbc_type_s; | ||
3627 | gops->gr.pagepool_default_size = gr_gv11b_pagepool_default_size; | ||
3628 | gops->gr.calc_global_ctx_buffer_size = | ||
3629 | gr_gv11b_calc_global_ctx_buffer_size; | ||
3630 | gops->gr.commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb; | ||
3631 | gops->gr.handle_sw_method = gr_gv11b_handle_sw_method; | ||
3632 | gops->gr.bundle_cb_defaults = gr_gv11b_bundle_cb_defaults; | ||
3633 | gops->gr.cb_size_default = gr_gv11b_cb_size_default; | ||
3634 | gops->gr.set_alpha_circular_buffer_size = | ||
3635 | gr_gv11b_set_alpha_circular_buffer_size; | ||
3636 | gops->gr.set_circular_buffer_size = | ||
3637 | gr_gv11b_set_circular_buffer_size; | ||
3638 | gops->gr.dump_gr_regs = gr_gv11b_dump_gr_status_regs; | ||
3639 | gops->gr.wait_empty = gr_gv11b_wait_empty; | ||
3640 | gops->gr.init_cyclestats = gr_gv11b_init_cyclestats; | ||
3641 | gops->gr.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask; | ||
3642 | gops->gr.get_access_map = gr_gv11b_get_access_map; | ||
3643 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | ||
3644 | gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception; | ||
3645 | gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; | ||
3646 | gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; | ||
3647 | gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; | ||
3648 | gops->gr.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions; | ||
3649 | gops->gr.pre_process_sm_exception = | ||
3650 | gr_gv11b_pre_process_sm_exception; | ||
3651 | gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; | ||
3652 | gops->gr.create_gr_sysfs = gr_gv11b_create_sysfs; | ||
3653 | gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping; | ||
3654 | gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle; | ||
3655 | gops->gr.program_zcull_mapping = gr_gv11b_program_zcull_mapping; | ||
3656 | gops->gr.commit_global_timeslice = gr_gv11b_commit_global_timeslice; | ||
3657 | gops->gr.init_sm_id_table = gr_gv11b_init_sm_id_table; | ||
3658 | gops->gr.load_smid_config = gr_gv11b_load_smid_config; | ||
3659 | gops->gr.program_sm_id_numbering = | ||
3660 | gr_gv11b_program_sm_id_numbering; | ||
3661 | gops->gr.commit_inst = gr_gv11b_commit_inst; | ||
3662 | gops->gr.restore_context_header = gv11b_restore_context_header; | ||
3663 | gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; | ||
3664 | gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; | ||
3665 | gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; | ||
3666 | gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; | ||
3667 | gops->gr.handle_gpc_gpccs_exception = | ||
3668 | gr_gv11b_handle_gpc_gpccs_exception; | ||
3669 | gops->gr.set_czf_bypass = NULL; | ||
3670 | gops->gr.handle_gpc_gpcmmu_exception = | ||
3671 | gr_gv11b_handle_gpc_gpcmmu_exception; | ||
3672 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; | ||
3673 | gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; | ||
3674 | gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; | ||
3675 | gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; | ||
3676 | gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; | ||
3677 | gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; | ||
3678 | gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; | ||
3679 | gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; | ||
3680 | gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; | ||
3681 | gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; | ||
3682 | gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; | ||
3683 | gops->gr.resume_all_sms = gv11b_gr_resume_all_sms; | ||
3684 | gops->gr.resume_from_pause = gv11b_gr_resume_from_pause; | ||
3685 | gops->gr.get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr; | ||
3686 | gops->gr.get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr; | ||
3687 | gops->gr.get_sm_no_lock_down_hww_global_esr_mask = | ||
3688 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask; | ||
3689 | gops->gr.lock_down_sm = gv11b_gr_lock_down_sm; | ||
3690 | gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down; | ||
3691 | gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; | ||
3692 | gops->gr.handle_tpc_sm_ecc_exception = | ||
3693 | gr_gv11b_handle_tpc_sm_ecc_exception; | ||
3694 | gops->gr.handle_tpc_mpc_exception = | ||
3695 | gr_gv11b_handle_tpc_mpc_exception; | ||
3696 | gops->gr.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf; | ||
3697 | gops->gr.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info; | ||
3698 | gops->gr.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs; | ||
3699 | gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs; | ||
3700 | gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs; | ||
3701 | gops->gr.access_smpc_reg = gv11b_gr_access_smpc_reg; | ||
3702 | gops->gr.decode_egpc_addr = gv11b_gr_decode_egpc_addr; | ||
3703 | gops->gr.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table; | ||
3704 | gops->gr.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num; | ||
3705 | gops->gr.get_egpc_base = gv11b_gr_get_egpc_base; | ||
3706 | gops->gr.is_egpc_addr = gv11b_gr_pri_is_egpc_addr; | ||
3707 | gops->gr.is_etpc_addr = gv11b_gr_pri_is_etpc_addr; | ||
3708 | gops->gr.init_gpc_mmu = gr_gv11b_init_gpc_mmu; | ||
3709 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 69148554..9adace63 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -30,6 +30,9 @@ struct zbc_s_table { | |||
30 | }; | 30 | }; |
31 | 31 | ||
32 | struct gk20a; | 32 | struct gk20a; |
33 | struct zbc_entry; | ||
34 | struct zbc_query_params; | ||
35 | struct channel_ctx_gk20a; | ||
33 | 36 | ||
34 | enum { | 37 | enum { |
35 | VOLTA_CHANNEL_GPFIFO_A = 0xC36F, | 38 | VOLTA_CHANNEL_GPFIFO_A = 0xC36F, |
@@ -59,11 +62,146 @@ enum { | |||
59 | 62 | ||
60 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 63 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
61 | 64 | ||
62 | void gv11b_init_gr(struct gk20a *g); | ||
63 | int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, | 65 | int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, |
64 | struct nvgpu_mem *mem); | 66 | struct nvgpu_mem *mem); |
65 | /*zcull*/ | 67 | /*zcull*/ |
66 | void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, | 68 | void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, |
67 | u32 *zcull_map_tiles); | 69 | u32 *zcull_map_tiles); |
68 | void gr_gv11b_create_sysfs(struct device *dev); | 70 | void gr_gv11b_create_sysfs(struct device *dev); |
71 | |||
72 | bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num); | ||
73 | bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num); | ||
74 | bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num); | ||
75 | void gr_gv11b_enable_hww_exceptions(struct gk20a *g); | ||
76 | void gr_gv11b_enable_exceptions(struct gk20a *g); | ||
77 | int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, | ||
78 | u32 gpc, u32 tpc, | ||
79 | bool *post_event, struct channel_gk20a *fault_ch, | ||
80 | u32 *hww_global_esr); | ||
81 | int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
82 | bool *post_event, struct channel_gk20a *fault_ch, | ||
83 | u32 *hww_global_esr); | ||
84 | int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, | ||
85 | u32 gpc_exception); | ||
86 | int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, | ||
87 | u32 gpc_exception); | ||
88 | void gr_gv11b_enable_gpc_exceptions(struct gk20a *g); | ||
89 | int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
90 | bool *post_event); | ||
91 | int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, | ||
92 | struct zbc_query_params *query_params); | ||
93 | bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, | ||
94 | struct zbc_entry *zbc_val, int *ret_val); | ||
95 | int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, | ||
96 | struct zbc_entry *stencil_val, u32 index); | ||
97 | int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, | ||
98 | struct gr_gk20a *gr); | ||
99 | int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr); | ||
100 | u32 gr_gv11b_pagepool_default_size(struct gk20a *g); | ||
101 | int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g); | ||
102 | int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | ||
103 | u32 class_num, u32 offset, u32 data); | ||
104 | void gr_gv11b_bundle_cb_defaults(struct gk20a *g); | ||
105 | void gr_gv11b_cb_size_default(struct gk20a *g); | ||
106 | void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data); | ||
107 | void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data); | ||
108 | int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | ||
109 | struct gk20a_debug_output *o); | ||
110 | int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, | ||
111 | u32 expect_delay); | ||
112 | void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | ||
113 | struct channel_ctx_gk20a *ch_ctx, | ||
114 | u64 addr, bool patch); | ||
115 | void gr_gv11b_init_cyclestats(struct gk20a *g); | ||
116 | void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | ||
117 | void gr_gv11b_get_access_map(struct gk20a *g, | ||
118 | u32 **whitelist, int *num_entries); | ||
119 | int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | ||
120 | u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, | ||
121 | bool sm_debugger_attached, struct channel_gk20a *fault_ch, | ||
122 | bool *early_exit, bool *ignore_debugger); | ||
123 | int gr_gv11b_handle_fecs_error(struct gk20a *g, | ||
124 | struct channel_gk20a *__ch, | ||
125 | struct gr_gk20a_isr_data *isr_data); | ||
126 | int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr); | ||
127 | int gr_gv11b_init_sw_veid_bundle(struct gk20a *g); | ||
128 | void gr_gv11b_detect_sm_arch(struct gk20a *g); | ||
129 | void gr_gv11b_init_sm_id_table(struct gk20a *g); | ||
130 | void gr_gv11b_program_sm_id_numbering(struct gk20a *g, | ||
131 | u32 gpc, u32 tpc, u32 smid); | ||
132 | int gr_gv11b_load_smid_config(struct gk20a *g); | ||
133 | int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); | ||
134 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, | ||
135 | struct channel_gk20a *c, bool patch); | ||
136 | void gv11b_restore_context_header(struct gk20a *g, | ||
137 | struct nvgpu_mem *ctxheader); | ||
138 | void gr_gv11b_write_zcull_ptr(struct gk20a *g, | ||
139 | struct nvgpu_mem *mem, u64 gpu_va); | ||
140 | void gr_gv11b_write_pm_ptr(struct gk20a *g, | ||
141 | struct nvgpu_mem *mem, u64 gpu_va); | ||
142 | void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); | ||
143 | void gr_gv11b_load_tpc_mask(struct gk20a *g); | ||
144 | void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, | ||
145 | struct nvgpu_mem *mem, u64 gpu_va); | ||
146 | int gr_gv11b_init_fs_state(struct gk20a *g); | ||
147 | void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | ||
148 | u32 *esr_sm_sel); | ||
149 | int gv11b_gr_sm_trigger_suspend(struct gk20a *g); | ||
150 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); | ||
151 | int gv11b_gr_update_sm_error_state(struct gk20a *g, | ||
152 | struct channel_gk20a *ch, u32 sm_id, | ||
153 | struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); | ||
154 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | ||
155 | struct channel_gk20a *ch, u64 sms, bool enable); | ||
156 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); | ||
157 | void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g); | ||
158 | bool gv11b_gr_sm_debugger_attached(struct gk20a *g); | ||
159 | void gv11b_gr_suspend_single_sm(struct gk20a *g, | ||
160 | u32 gpc, u32 tpc, u32 sm, | ||
161 | u32 global_esr_mask, bool check_errors); | ||
162 | void gv11b_gr_suspend_all_sms(struct gk20a *g, | ||
163 | u32 global_esr_mask, bool check_errors); | ||
164 | void gv11b_gr_resume_single_sm(struct gk20a *g, | ||
165 | u32 gpc, u32 tpc, u32 sm); | ||
166 | void gv11b_gr_resume_all_sms(struct gk20a *g); | ||
167 | int gv11b_gr_resume_from_pause(struct gk20a *g); | ||
168 | u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, | ||
169 | u32 gpc, u32 tpc, u32 sm); | ||
170 | u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, | ||
171 | u32 gpc, u32 tpc, u32 sm); | ||
172 | u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); | ||
173 | int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, | ||
174 | u32 gpc, u32 tpc, u32 sm, | ||
175 | u32 global_esr_mask, bool check_errors); | ||
176 | int gv11b_gr_lock_down_sm(struct gk20a *g, | ||
177 | u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, | ||
178 | bool check_errors); | ||
179 | void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | ||
180 | u32 global_esr); | ||
181 | int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, | ||
182 | u32 gpc, u32 tpc, bool *post_event); | ||
183 | void gv11b_gr_init_ovr_sm_dsm_perf(void); | ||
184 | void gv11b_gr_init_sm_dsm_reg_info(void); | ||
185 | void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, | ||
186 | u32 *num_sm_dsm_perf_regs, | ||
187 | u32 **sm_dsm_perf_regs, | ||
188 | u32 *perf_register_stride); | ||
189 | void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | ||
190 | u32 *num_sm_dsm_perf_ctrl_regs, | ||
191 | u32 **sm_dsm_perf_ctrl_regs, | ||
192 | u32 *ctrl_register_stride); | ||
193 | void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, | ||
194 | u32 **ovr_perf_regs); | ||
195 | void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset); | ||
196 | bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr); | ||
197 | bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr); | ||
198 | void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, | ||
199 | u32 *egpc_num, u32 *etpc_num); | ||
200 | int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, | ||
201 | u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); | ||
202 | void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, | ||
203 | u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t); | ||
204 | u32 gv11b_gr_get_egpc_base(struct gk20a *g); | ||
205 | void gr_gv11b_init_gpc_mmu(struct gk20a *g); | ||
206 | |||
69 | #endif | 207 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4b64d44d..0c5776f0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include "gk20a/regops_gk20a.h" | 32 | #include "gk20a/regops_gk20a.h" |
33 | #include "gk20a/fb_gk20a.h" | 33 | #include "gk20a/fb_gk20a.h" |
34 | #include "gk20a/pmu_gk20a.h" | 34 | #include "gk20a/pmu_gk20a.h" |
35 | #include "gk20a/gr_gk20a.h" | ||
35 | 36 | ||
36 | #include "gm20b/ltc_gm20b.h" | 37 | #include "gm20b/ltc_gm20b.h" |
37 | #include "gm20b/gr_gm20b.h" | 38 | #include "gm20b/gr_gm20b.h" |
@@ -51,6 +52,7 @@ | |||
51 | #include "gp10b/fb_gp10b.h" | 52 | #include "gp10b/fb_gp10b.h" |
52 | #include "gp10b/mm_gp10b.h" | 53 | #include "gp10b/mm_gp10b.h" |
53 | #include "gp10b/pmu_gp10b.h" | 54 | #include "gp10b/pmu_gp10b.h" |
55 | #include "gp10b/gr_gp10b.h" | ||
54 | 56 | ||
55 | #include "gp106/pmu_gp106.h" | 57 | #include "gp106/pmu_gp106.h" |
56 | 58 | ||
@@ -194,6 +196,150 @@ static const struct gpu_ops gv11b_ops = { | |||
194 | .isr_nonstall = gp10b_ce_nonstall_isr, | 196 | .isr_nonstall = gp10b_ce_nonstall_isr, |
195 | .get_num_pce = gv11b_ce_get_num_pce, | 197 | .get_num_pce = gv11b_ce_get_num_pce, |
196 | }, | 198 | }, |
199 | .gr = { | ||
200 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | ||
201 | .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, | ||
202 | .cb_size_default = gr_gv11b_cb_size_default, | ||
203 | .calc_global_ctx_buffer_size = | ||
204 | gr_gv11b_calc_global_ctx_buffer_size, | ||
205 | .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, | ||
206 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
207 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
208 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
209 | .handle_sw_method = gr_gv11b_handle_sw_method, | ||
210 | .set_alpha_circular_buffer_size = | ||
211 | gr_gv11b_set_alpha_circular_buffer_size, | ||
212 | .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, | ||
213 | .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, | ||
214 | .is_valid_class = gr_gv11b_is_valid_class, | ||
215 | .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, | ||
216 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | ||
217 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | ||
218 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | ||
219 | .init_fs_state = gr_gv11b_init_fs_state, | ||
220 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | ||
221 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
222 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | ||
223 | .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, | ||
224 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | ||
225 | .free_channel_ctx = gk20a_free_channel_ctx, | ||
226 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | ||
227 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | ||
228 | .get_zcull_info = gr_gk20a_get_zcull_info, | ||
229 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
230 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
231 | .detect_sm_arch = gr_gv11b_detect_sm_arch, | ||
232 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
233 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
234 | .zbc_set_table = gk20a_gr_zbc_set_table, | ||
235 | .zbc_query_table = gr_gk20a_query_zbc, | ||
236 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
237 | .add_zbc = gr_gk20a_add_zbc, | ||
238 | .pagepool_default_size = gr_gv11b_pagepool_default_size, | ||
239 | .init_ctx_state = gr_gp10b_init_ctx_state, | ||
240 | .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, | ||
241 | .free_gr_ctx = gr_gp10b_free_gr_ctx, | ||
242 | .update_ctxsw_preemption_mode = | ||
243 | gr_gp10b_update_ctxsw_preemption_mode, | ||
244 | .dump_gr_regs = gr_gv11b_dump_gr_status_regs, | ||
245 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
246 | .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, | ||
247 | .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, | ||
248 | .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, | ||
249 | .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, | ||
250 | .get_max_fbps_count = gr_gm20b_get_max_fbps_count, | ||
251 | .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, | ||
252 | .wait_empty = gr_gv11b_wait_empty, | ||
253 | .init_cyclestats = gr_gv11b_init_cyclestats, | ||
254 | .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, | ||
255 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
256 | .bpt_reg_info = gv11b_gr_bpt_reg_info, | ||
257 | .get_access_map = gr_gv11b_get_access_map, | ||
258 | .handle_fecs_error = gr_gv11b_handle_fecs_error, | ||
259 | .handle_sm_exception = gr_gk20a_handle_sm_exception, | ||
260 | .handle_tex_exception = gr_gv11b_handle_tex_exception, | ||
261 | .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, | ||
262 | .enable_exceptions = gr_gv11b_enable_exceptions, | ||
263 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
264 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | ||
265 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | ||
266 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | ||
267 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | ||
268 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | ||
269 | .suspend_contexts = gr_gp10b_suspend_contexts, | ||
270 | .resume_contexts = gr_gk20a_resume_contexts, | ||
271 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
272 | .fuse_override = gp10b_gr_fuse_override, | ||
273 | .init_sm_id_table = gr_gv11b_init_sm_id_table, | ||
274 | .load_smid_config = gr_gv11b_load_smid_config, | ||
275 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | ||
276 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
277 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
278 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
279 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
280 | .setup_rop_mapping = gr_gv11b_setup_rop_mapping, | ||
281 | .program_zcull_mapping = gr_gv11b_program_zcull_mapping, | ||
282 | .commit_global_timeslice = gr_gv11b_commit_global_timeslice, | ||
283 | .commit_inst = gr_gv11b_commit_inst, | ||
284 | .write_zcull_ptr = gr_gv11b_write_zcull_ptr, | ||
285 | .write_pm_ptr = gr_gv11b_write_pm_ptr, | ||
286 | .init_elcg_mode = gr_gv11b_init_elcg_mode, | ||
287 | .load_tpc_mask = gr_gv11b_load_tpc_mask, | ||
288 | .inval_icache = gr_gk20a_inval_icache, | ||
289 | .trigger_suspend = gv11b_gr_sm_trigger_suspend, | ||
290 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
291 | .resume_from_pause = gv11b_gr_resume_from_pause, | ||
292 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
293 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
294 | .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, | ||
295 | .sm_debugger_attached = gv11b_gr_sm_debugger_attached, | ||
296 | .suspend_single_sm = gv11b_gr_suspend_single_sm, | ||
297 | .suspend_all_sms = gv11b_gr_suspend_all_sms, | ||
298 | .resume_single_sm = gv11b_gr_resume_single_sm, | ||
299 | .resume_all_sms = gv11b_gr_resume_all_sms, | ||
300 | .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, | ||
301 | .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, | ||
302 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
303 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
304 | .lock_down_sm = gv11b_gr_lock_down_sm, | ||
305 | .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, | ||
306 | .clear_sm_hww = gv11b_gr_clear_sm_hww, | ||
307 | .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, | ||
308 | .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, | ||
309 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
310 | .set_boosted_ctx = gr_gp10b_set_boosted_ctx, | ||
311 | .set_preemption_mode = gr_gp10b_set_preemption_mode, | ||
312 | .set_czf_bypass = NULL, | ||
313 | .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, | ||
314 | .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, | ||
315 | .init_preemption_state = NULL, | ||
316 | .update_boosted_ctx = gr_gp10b_update_boosted_ctx, | ||
317 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
318 | .create_gr_sysfs = gr_gv11b_create_sysfs, | ||
319 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, | ||
320 | .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, | ||
321 | .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, | ||
322 | .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, | ||
323 | .zbc_s_query_table = gr_gv11b_zbc_s_query_table, | ||
324 | .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, | ||
325 | .restore_context_header = gv11b_restore_context_header, | ||
326 | .handle_gpc_gpcmmu_exception = | ||
327 | gr_gv11b_handle_gpc_gpcmmu_exception, | ||
328 | .add_zbc_type_s = gr_gv11b_add_zbc_type_s, | ||
329 | .get_egpc_base = gv11b_gr_get_egpc_base, | ||
330 | .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, | ||
331 | .handle_gpc_gpccs_exception = | ||
332 | gr_gv11b_handle_gpc_gpccs_exception, | ||
333 | .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, | ||
334 | .access_smpc_reg = gv11b_gr_access_smpc_reg, | ||
335 | .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, | ||
336 | .add_zbc_s = gr_gv11b_add_zbc_stencil, | ||
337 | .handle_gcc_exception = gr_gv11b_handle_gcc_exception, | ||
338 | .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, | ||
339 | .handle_tpc_sm_ecc_exception = | ||
340 | gr_gv11b_handle_tpc_sm_ecc_exception, | ||
341 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | ||
342 | }, | ||
197 | .fb = { | 343 | .fb = { |
198 | .reset = gv11b_fb_reset, | 344 | .reset = gv11b_fb_reset, |
199 | .init_hw = gk20a_fb_init_hw, | 345 | .init_hw = gk20a_fb_init_hw, |
@@ -490,6 +636,7 @@ int gv11b_init_hal(struct gk20a *g) | |||
490 | 636 | ||
491 | gops->ltc = gv11b_ops.ltc; | 637 | gops->ltc = gv11b_ops.ltc; |
492 | gops->ce2 = gv11b_ops.ce2; | 638 | gops->ce2 = gv11b_ops.ce2; |
639 | gops->gr = gv11b_ops.gr; | ||
493 | gops->fb = gv11b_ops.fb; | 640 | gops->fb = gv11b_ops.fb; |
494 | gops->clock_gating = gv11b_ops.clock_gating; | 641 | gops->clock_gating = gv11b_ops.clock_gating; |
495 | gops->fifo = gv11b_ops.fifo; | 642 | gops->fifo = gv11b_ops.fifo; |
@@ -541,6 +688,8 @@ int gv11b_init_hal(struct gk20a *g) | |||
541 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 688 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
542 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; | 689 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; |
543 | gops->pmu.is_priv_load = gp10b_is_priv_load; | 690 | gops->pmu.is_priv_load = gp10b_is_priv_load; |
691 | |||
692 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | ||
544 | } else { | 693 | } else { |
545 | /* Inherit from gk20a */ | 694 | /* Inherit from gk20a */ |
546 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | 695 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, |
@@ -549,9 +698,9 @@ int gv11b_init_hal(struct gk20a *g) | |||
549 | gops->pmu.load_lsfalcon_ucode = NULL; | 698 | gops->pmu.load_lsfalcon_ucode = NULL; |
550 | gops->pmu.init_wpr_region = NULL; | 699 | gops->pmu.init_wpr_region = NULL; |
551 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; | 700 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; |
552 | } | ||
553 | 701 | ||
554 | gv11b_init_gr(g); | 702 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; |
703 | } | ||
555 | 704 | ||
556 | gv11b_init_uncompressed_kind_map(); | 705 | gv11b_init_uncompressed_kind_map(); |
557 | gv11b_init_kind_attr(); | 706 | gv11b_init_kind_attr(); |