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author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-08-15 18:25:19 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-26 20:29:18 -0400 |
commit | 84fe49a42100288d9e476f70f888c18bc8066ec7 (patch) | |
tree | 2f22fdb6189b02a84b4aabccb2d5f14c8ef6006a | |
parent | 8d8ae609ad8b2042b3b8e388b02efa79b6c57a18 (diff) |
gpu: nvgpu: fix handling of EGPC_ETPC_SM addresses
Added new defines for following litter values:
GPU_LIT_SMPC_PRI_BASE
GPU_LIT_SMPC_PRI_SHARED_BASE
GPU_LIT_SMPC_PRI_UNIQUE_BASE9
GPU_LIT_SMPC_PRI_STRIDE
Calculate offsets for ctx operations considering
sm per tpc. Following functions are modified for this:
gr_gk20a_get_ctx_buffer_offsets
gr_gk20a_get_pm_ctx_buffer_offsets
__gr_gk20a_exec_ctx_ops
Bug 200337994
Change-Id: I3a4ca470a4107d3078b708f38601762626ce1bf1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539069
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 12 |
2 files changed, 13 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index dbf36f5c..8dabee63 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -129,6 +129,10 @@ enum gk20a_cbc_op { | |||
129 | #define GPU_LIT_FBPA_BASE 24 | 129 | #define GPU_LIT_FBPA_BASE 24 |
130 | #define GPU_LIT_FBPA_SHARED_BASE 25 | 130 | #define GPU_LIT_FBPA_SHARED_BASE 25 |
131 | #define GPU_LIT_SM_PRI_STRIDE 26 | 131 | #define GPU_LIT_SM_PRI_STRIDE 26 |
132 | #define GPU_LIT_SMPC_PRI_BASE 27 | ||
133 | #define GPU_LIT_SMPC_PRI_SHARED_BASE 28 | ||
134 | #define GPU_LIT_SMPC_PRI_UNIQUE_BASE 29 | ||
135 | #define GPU_LIT_SMPC_PRI_STRIDE 30 | ||
132 | 136 | ||
133 | #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) | 137 | #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) |
134 | 138 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 4c4f8253..679b8492 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -6363,7 +6363,9 @@ int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g, | |||
6363 | u32 num_registers = 0; | 6363 | u32 num_registers = 0; |
6364 | int err = 0; | 6364 | int err = 0; |
6365 | struct gr_gk20a *gr = &g->gr; | 6365 | struct gr_gk20a *gr = &g->gr; |
6366 | u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count; | 6366 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); |
6367 | u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count * | ||
6368 | sm_per_tpc; | ||
6367 | 6369 | ||
6368 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); | 6370 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); |
6369 | 6371 | ||
@@ -6441,7 +6443,9 @@ int gr_gk20a_get_pm_ctx_buffer_offsets(struct gk20a *g, | |||
6441 | u32 num_registers = 0; | 6443 | u32 num_registers = 0; |
6442 | int err = 0; | 6444 | int err = 0; |
6443 | struct gr_gk20a *gr = &g->gr; | 6445 | struct gr_gk20a *gr = &g->gr; |
6444 | u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count; | 6446 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); |
6447 | u32 potential_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count * | ||
6448 | sm_per_tpc; | ||
6445 | 6449 | ||
6446 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); | 6450 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr); |
6447 | 6451 | ||
@@ -7719,7 +7723,9 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
7719 | struct nvgpu_mem *current_mem = NULL; | 7723 | struct nvgpu_mem *current_mem = NULL; |
7720 | u32 i, j, offset, v; | 7724 | u32 i, j, offset, v; |
7721 | struct gr_gk20a *gr = &g->gr; | 7725 | struct gr_gk20a *gr = &g->gr; |
7722 | u32 max_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count; | 7726 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); |
7727 | u32 max_offsets = gr->max_gpc_count * gr->max_tpc_per_gpc_count * | ||
7728 | sm_per_tpc; | ||
7723 | u32 *offsets = NULL; | 7729 | u32 *offsets = NULL; |
7724 | u32 *offset_addrs = NULL; | 7730 | u32 *offset_addrs = NULL; |
7725 | u32 ctx_op_nr, num_ctx_ops[2] = {num_ctx_wr_ops, num_ctx_rd_ops}; | 7731 | u32 ctx_op_nr, num_ctx_ops[2] = {num_ctx_wr_ops, num_ctx_rd_ops}; |