gpu: nvgpu: gv11b: Reorg fifo HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the fifo
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522554
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

3 files changed, 163 insertions, 90 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index b0270150..e210d40d 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -59,7 +59,7 @@ static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v)
         gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v);
 }
 
-static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
+void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
 {
 
         u32 runlist_entry_0 = ram_rl_entry_type_tsg_v();
@@ -85,7 +85,7 @@ static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
 
 }
 
-static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
+void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
 {
         struct gk20a *g = c->g;
         u32 addr_lo, addr_hi;
@@ -126,7 +126,7 @@ static void gv11b_userd_writeback_config(struct gk20a *g)
 
 }
 
-static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
+int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
                 u64 gpfifo_base, u32 gpfifo_entries,
                 unsigned long acquire_timeout, u32 flags)
 {
@@ -219,7 +219,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
                 usermode_notify_channel_pending_id_f(hw_chid));
 }
 
-static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c)
+u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c)
 {
         struct nvgpu_mem *userd_mem = &g->fifo.userd;
         u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32));
@@ -228,7 +228,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c)
                         offset + ram_userd_gp_get_w());
 }
 
-static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c)
+u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c)
 {
         struct nvgpu_mem *userd_mem = &g->fifo.userd;
         u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32));
@@ -238,7 +238,7 @@ static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c)
         return ((u64)hi << 32) | lo;
 }
 
-static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c)
+void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c)
 {
         struct nvgpu_mem *userd_mem = &g->fifo.userd;
         u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32));
@@ -251,24 +251,24 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c)
         gv11b_ring_channel_doorbell(c);
 }
 
-static void channel_gv11b_unbind(struct channel_gk20a *ch)
+void channel_gv11b_unbind(struct channel_gk20a *ch)
 {
         gk20a_dbg_fn("");
 
         gk20a_fifo_channel_unbind(ch);
 }
 
-static u32 gv11b_fifo_get_num_fifos(struct gk20a *g)
+u32 gv11b_fifo_get_num_fifos(struct gk20a *g)
 {
         return ccsr_channel__size_1_v();
 }
 
-static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid)
+bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid)
 {
         return (engine_subid == gmmu_fault_client_type_gpc_v());
 }
 
-static void gv11b_dump_channel_status_ramfc(struct gk20a *g,
+void gv11b_dump_channel_status_ramfc(struct gk20a *g,
                                      struct gk20a_debug_output *o,
                                      u32 chid,
                                      struct ch_state *ch_state)
@@ -322,7 +322,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g,
         gk20a_debug_output(o, "\n");
 }
 
-static void gv11b_dump_eng_status(struct gk20a *g,
+void gv11b_dump_eng_status(struct gk20a *g,
                                  struct gk20a_debug_output *o)
 {
         u32 i, host_num_engines;
@@ -355,7 +355,7 @@ static void gv11b_dump_eng_status(struct gk20a *g,
         gk20a_debug_output(o, "\n");
 }
 
-static u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g)
+u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g)
 {
         u32 intr_0_error_mask =
                 fifo_intr_0_bind_error_pending_f() |
@@ -698,7 +698,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g,
         return ret;
 }
 
-static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
+int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
                  unsigned int id_type, unsigned int timeout_rc_type)
 {
         struct fifo_gk20a *f = &g->fifo;
@@ -747,7 +747,7 @@ static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
         return ret;
 }
 
-static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid)
+int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid)
 {
         struct fifo_gk20a *f = &g->fifo;
         u32 tsgid;
@@ -784,7 +784,7 @@ static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask)
         return ret;
 }
 
-static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid)
+int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid)
 {
         struct fifo_gk20a *f = &g->fifo;
         u32 ret = 0;
@@ -868,7 +868,7 @@ static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id,
 }
 
 
-static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id,
+int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id,
                          unsigned int id_type, unsigned int timeout_rc_type)
 {
         struct fifo_gk20a *f = &g->fifo;
@@ -906,7 +906,7 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id,
 
 }
 
-static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
+void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
                         u32 id, unsigned int id_type, unsigned int rc_type,
                          struct mmu_fault_info *mmfault)
 {
@@ -1058,7 +1058,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
                 nvgpu_pmu_enable_elpg(g);
 }
 
-static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
+void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
 {
         /*
          * These are all errors which indicate something really wrong
@@ -1118,7 +1118,7 @@ static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g)
         return intr_0_en_mask;
 }
 
-static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
+int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
 {
         u32 intr_stall;
         u32 mask;
@@ -1232,7 +1232,7 @@ static const char *const gv11b_sched_error_str[] = {
         "bad_tsg",
 };
 
-static bool gv11b_fifo_handle_sched_error(struct gk20a *g)
+bool gv11b_fifo_handle_sched_error(struct gk20a *g)
 {
         u32 sched_error;
 
@@ -1348,7 +1348,7 @@ static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id)
         return tsgid;
 }
 
-static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr)
+bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr)
 {
         bool ret = false;
         u32 tsgid = FIFO_INVAL_TSG_ID;
@@ -1411,7 +1411,7 @@ static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr)
         return ret;
 }
 
-static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g,
+unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g,
                         u32 pbdma_id, u32 pbdma_intr_0,
                         u32 *handled, u32 *error_notifier)
 {
@@ -1460,7 +1460,7 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g,
  * will have to be destroyed.
  */
 
-static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g,
+unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g,
                         u32 pbdma_id, u32 pbdma_intr_1,
                         u32 *handled, u32 *error_notifier)
 {
@@ -1537,7 +1537,7 @@ unsigned int gv11b_fifo_get_eng_method_buffer_size(struct gk20a *g)
         return buffer_size;
 }
 
-static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g,
+void gv11b_fifo_init_eng_method_buffers(struct gk20a *g,
                                         struct tsg_gk20a *tsg)
 {
         struct vm_gk20a *vm = g->mm.bar2.vm;
@@ -1577,7 +1577,7 @@ static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g,
 
 }
 
-static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
+void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
                                         struct tsg_gk20a *tsg)
 {
         struct vm_gk20a *vm = g->mm.bar2.vm;
@@ -1596,7 +1596,7 @@ static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
 }
 
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
-static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
+int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
                         u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
 {
         struct page **pages;
@@ -1631,14 +1631,14 @@ static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
         return err;
 }
 
-static void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c,
+void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c,
                                         struct nvgpu_mem *syncpt_buf)
 {
         nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va);
         nvgpu_dma_free(c->g, syncpt_buf);
 }
 
-static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g,
+void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g,
                 struct priv_cmd_entry *cmd, u32 off,
                 u32 id, u32 thresh, u64 gpu_va_base)
 {
@@ -1668,12 +1668,12 @@ static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g,
         nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12));
 }
 
-static u32 gv11b_fifo_get_syncpt_wait_cmd_size(void)
+u32 gv11b_fifo_get_syncpt_wait_cmd_size(void)
 {
         return 8;
 }
 
-static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g,
+void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g,
                 bool wfi_cmd, struct priv_cmd_entry *cmd,
                 u32 id, u64 gpu_va_base)
 {
@@ -1706,13 +1706,13 @@ static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g,
         nvgpu_mem_wr32(g, cmd->mem, off++, 0);
 }
 
-static u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd)
+u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd)
 {
         return 9;
 }
 #endif /* CONFIG_TEGRA_GK20A_NVHOST */
 
-static int gv11b_init_fifo_setup_hw(struct gk20a *g)
+int gv11b_init_fifo_setup_hw(struct gk20a *g)
 {
         struct fifo_gk20a *f = &g->fifo;
 
@@ -1790,58 +1790,3 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
         else
                 *pbdma_id = FIFO_INVAL_PBDMA_ID;
 }
-
-void gv11b_init_fifo(struct gpu_ops *gops)
-{
-        gp10b_init_fifo(gops);
-        /* for gv11b no need to do any thing special for fifo hw setup */
-        gops->fifo.init_fifo_setup_hw = gv11b_init_fifo_setup_hw;
-        gops->fifo.runlist_entry_size = ram_rl_entry_size_v;
-        gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry;
-        gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry;
-        gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos;
-        gops->fifo.userd_gp_get = gv11b_userd_gp_get;
-        gops->fifo.userd_gp_put = gv11b_userd_gp_put;
-        gops->fifo.userd_pb_get = gv11b_userd_pb_get;
-        gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc;
-        gops->fifo.resetup_ramfc = NULL;
-        gops->fifo.unbind_channel = channel_gv11b_unbind;
-        gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
-        gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header;
-        gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v;
-        gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc;
-        gops->fifo.trigger_mmu_fault = NULL;
-        gops->fifo.get_mmu_fault_info = NULL;
-        gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
-        gops->fifo.dump_eng_status = gv11b_dump_eng_status;
-        gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc;
-        gops->fifo.intr_0_error_mask = gv11b_fifo_intr_0_error_mask;
-        gops->fifo.preempt_channel = gv11b_fifo_preempt_channel;
-        gops->fifo.preempt_tsg = gv11b_fifo_preempt_tsg;
-        gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending;
-        gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg;
-        gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs;
-        gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw;
-        gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg;
-        gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error;
-        gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout;
-        gops->fifo.handle_pbdma_intr_0 =
-                         gv11b_fifo_handle_pbdma_intr_0;
-        gops->fifo.handle_pbdma_intr_1 =
-                         gv11b_fifo_handle_pbdma_intr_1;
-        gops->fifo.init_eng_method_buffers =
-                        gv11b_fifo_init_eng_method_buffers;
-        gops->fifo.deinit_eng_method_buffers =
-                        gv11b_fifo_deinit_eng_method_buffers;
-#ifdef CONFIG_TEGRA_GK20A_NVHOST
-        gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf;
-        gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf;
-        gops->fifo.add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd;
-        gops->fifo.get_syncpt_wait_cmd_size =
-                                gv11b_fifo_get_syncpt_wait_cmd_size;
-        gops->fifo.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd;
-        gops->fifo.get_syncpt_incr_cmd_size =
-                                gv11b_fifo_get_syncpt_incr_cmd_size;
-#endif
-
-}
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
index 8a2b32f8..3fb2f6e9 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
@@ -40,10 +40,66 @@
 #define CHANNEL_INFO_VEID0              0
 
 struct gpu_ops;
-void gv11b_init_fifo(struct gpu_ops *gops);
+
 void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
                         struct channel_gk20a *refch,
                         u32 faulted_pbdma, u32 faulted_engine);
 void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
         u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id);
+
+void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist);
+void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist);
+int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
+                u64 gpfifo_base, u32 gpfifo_entries,
+                unsigned long acquire_timeout, u32 flags);
+u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c);
+u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c);
+void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c);
+void channel_gv11b_unbind(struct channel_gk20a *ch);
+u32 gv11b_fifo_get_num_fifos(struct gk20a *g);
+bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid);
+void gv11b_dump_channel_status_ramfc(struct gk20a *g,
+                                     struct gk20a_debug_output *o,
+                                     u32 chid,
+                                     struct ch_state *ch_state);
+void gv11b_dump_eng_status(struct gk20a *g,
+                                 struct gk20a_debug_output *o);
+u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g);
+int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
+                 unsigned int id_type, unsigned int timeout_rc_type);
+int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid);
+int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid);
+int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id,
+                         unsigned int id_type, unsigned int timeout_rc_type);
+void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
+                        u32 id, unsigned int id_type, unsigned int rc_type,
+                         struct mmu_fault_info *mmfault);
+void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
+int gv11b_init_fifo_reset_enable_hw(struct gk20a *g);
+bool gv11b_fifo_handle_sched_error(struct gk20a *g);
+bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr);
+unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g,
+                        u32 pbdma_id, u32 pbdma_intr_0,
+                        u32 *handled, u32 *error_notifier);
+unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g,
+                        u32 pbdma_id, u32 pbdma_intr_1,
+                        u32 *handled, u32 *error_notifier);
+void gv11b_fifo_init_eng_method_buffers(struct gk20a *g,
+                                        struct tsg_gk20a *tsg);
+void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
+                                        struct tsg_gk20a *tsg);
+int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
+                        u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
+void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c,
+                                        struct nvgpu_mem *syncpt_buf);
+void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g,
+                struct priv_cmd_entry *cmd, u32 off,
+                u32 id, u32 thresh, u64 gpu_va_base);
+u32 gv11b_fifo_get_syncpt_wait_cmd_size(void);
+void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g,
+                bool wfi_cmd, struct priv_cmd_entry *cmd,
+                u32 id, u64 gpu_va_base);
+u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd);
+int gv11b_init_fifo_setup_hw(struct gk20a *g);
+
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 8dc9900a..b6c17c7d 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -20,6 +20,7 @@
 #include <linux/tegra_gpu_t19x.h>
 
 #include "gk20a/gk20a.h"
+#include "gk20a/fifo_gk20a.h"
 #include "gk20a/css_gr_gk20a.h"
 #include "gk20a/mc_gk20a.h"
 #include "gk20a/dbg_gpu_gk20a.h"
@@ -29,10 +30,12 @@
 
 #include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
+#include "gm20b/fifo_gm20b.h"
 
 #include "gp10b/ltc_gp10b.h"
 #include "gp10b/mc_gp10b.h"
 #include "gp10b/priv_ring_gp10b.h"
+#include "gp10b/fifo_gp10b.h"
 
 #include "hal_gv11b.h"
 #include "gr_gv11b.h"
@@ -49,10 +52,14 @@
 #include "fifo_gv11b.h"
 #include "gv11b_gating_reglist.h"
 #include "regops_gv11b.h"
+#include "subctx_gv11b.h"
 
 #include <nvgpu/debug.h>
 
 #include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 
 static int gv11b_get_litter_value(struct gk20a *g, int value)
 {
@@ -202,6 +209,72 @@ static const struct gpu_ops gv11b_ops = {
                 .pg_gr_load_gating_prod =
                         gr_gv11b_pg_gr_load_gating_prod,
         },
+        .fifo = {
+                .init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
+                .bind_channel = channel_gm20b_bind,
+                .unbind_channel = channel_gv11b_unbind,
+                .disable_channel = gk20a_fifo_disable_channel,
+                .enable_channel = gk20a_fifo_enable_channel,
+                .alloc_inst = gk20a_fifo_alloc_inst,
+                .free_inst = gk20a_fifo_free_inst,
+                .setup_ramfc = channel_gv11b_setup_ramfc,
+                .channel_set_priority = gk20a_fifo_set_priority,
+                .channel_set_timeslice = gk20a_fifo_set_timeslice,
+                .default_timeslice_us = gk20a_fifo_default_timeslice_us,
+                .setup_userd = gk20a_fifo_setup_userd,
+                .userd_gp_get = gv11b_userd_gp_get,
+                .userd_gp_put = gv11b_userd_gp_put,
+                .userd_pb_get = gv11b_userd_pb_get,
+                .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
+                .preempt_channel = gv11b_fifo_preempt_channel,
+                .preempt_tsg = gv11b_fifo_preempt_tsg,
+                .update_runlist = gk20a_fifo_update_runlist,
+                .trigger_mmu_fault = NULL,
+                .get_mmu_fault_info = NULL,
+                .wait_engine_idle = gk20a_fifo_wait_engine_idle,
+                .get_num_fifos = gv11b_fifo_get_num_fifos,
+                .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
+                .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
+                .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
+                .force_reset_ch = gk20a_fifo_force_reset_ch,
+                .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
+                .device_info_data_parse = gp10b_device_info_data_parse,
+                .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
+                .init_engine_info = gk20a_fifo_init_engine_info,
+                .runlist_entry_size = ram_rl_entry_size_v,
+                .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
+                .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
+                .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
+                .dump_pbdma_status = gk20a_dump_pbdma_status,
+                .dump_eng_status = gv11b_dump_eng_status,
+                .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
+                .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
+                .is_preempt_pending = gv11b_fifo_is_preempt_pending,
+                .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
+                .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
+                .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
+                .handle_sched_error = gv11b_fifo_handle_sched_error,
+                .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
+                .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
+                .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
+                .deinit_eng_method_buffers =
+                        gv11b_fifo_deinit_eng_method_buffers,
+                .tsg_bind_channel = gk20a_tsg_bind_channel,
+                .tsg_unbind_channel = gk20a_tsg_unbind_channel,
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+                .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
+                .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
+                .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
+                .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
+                .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
+                .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
+#endif
+                .resetup_ramfc = NULL,
+                .device_info_fault_id = top_device_info_data_fault_id_enum_v,
+                .free_channel_ctx_header = gv11b_free_subctx_header,
+                .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
+                .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
+        },
         .mc = {
                 .intr_enable = mc_gv11b_intr_enable,
                 .intr_unit_config = mc_gp10b_intr_unit_config,
@@ -267,6 +340,7 @@ int gv11b_init_hal(struct gk20a *g)
 
         gops->ltc = gv11b_ops.ltc;
         gops->clock_gating = gv11b_ops.clock_gating;
+        gops->fifo = gv11b_ops.fifo;
         gops->mc = gv11b_ops.mc;
         gops->debug = gv11b_ops.debug;
         gops->dbg_session_ops = gv11b_ops.dbg_session_ops;
@@ -289,14 +363,12 @@ int gv11b_init_hal(struct gk20a *g)
         gv11b_init_gr(gops);
         gv11b_init_fecs_trace_ops(gops);
         gv11b_init_fb(gops);
-        gv11b_init_fifo(gops);
         gv11b_init_ce(gops);
         gv11b_init_gr_ctx(gops);
         gv11b_init_mm(gops);
         gv11b_init_pmu_ops(gops);
         gv11b_init_regops(gops);
         gv11b_init_therm_ops(gops);
-        gk20a_init_tsg_ops(gops);
 
         g->name = "gv11b";