gpu: nvgpu: vgpu: add channel interleave support

Update vgpu back-end to send channel interleave request
to server.

JIRA VFND-1313
Bug 1729664

Change-Id: I2433aef485135ae9222dec238e25aedc19257744
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/1028976
(cherry picked from commit df3c5dc410839d126cc0574064d23e58102689b8)
Reviewed-on: http://git-master/r/1026049
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 40 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index b4bb7f38..a7e9eed8 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -541,6 +541,35 @@ static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority)
         return err ? err : msg.ret;
 }
 
+static int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
+                                        u32 id,
+                                        bool is_tsg,
+                                        u32 runlist_id,
+                                        u32 new_level)
+{
+        struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+        struct tegra_vgpu_cmd_msg msg;
+        struct tegra_vgpu_channel_runlist_interleave_params *p =
+                        &msg.params.channel_interleave;
+        struct channel_gk20a *ch;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        /* FIXME: add support for TSGs */
+        if (is_tsg)
+                return -ENOSYS;
+
+        ch = &g->fifo.channel[id];
+        msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE;
+        msg.handle = platform->virt_handle;
+        p->handle = ch->virt_ctx;
+        p->level = new_level;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        WARN_ON(err || msg.ret);
+        return err ? err : msg.ret;
+}
+
 static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g,
                 struct channel_gk20a *ch)
 {
@@ -626,5 +655,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops)
         gops->fifo.update_runlist = vgpu_fifo_update_runlist;
         gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle;
         gops->fifo.channel_set_priority = vgpu_channel_set_priority;
+        gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave;
 }
-
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 280ca9c0..5f697e78 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -1,7 +1,7 @@
 /*
  * Tegra GPU Virtualization Interfaces to Server
  *
- * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -74,7 +74,8 @@ enum {
         TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE,
         TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE,
         TEGRA_VGPU_CMD_REG_OPS,
-        TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY
+        TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY,
+        TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE
 };
 
 struct tegra_vgpu_connect_params {
@@ -298,6 +299,12 @@ struct tegra_vgpu_channel_priority_params {
         u32 priority;
 };
 
+/* level follows nvgpu.h definitions */
+struct tegra_vgpu_channel_runlist_interleave_params {
+        u64 handle;
+        u32 level;
+};
+
 struct tegra_vgpu_cmd_msg {
         u32 cmd;
         int ret;
@@ -326,6 +333,7 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_sm_debug_mode sm_debug_mode;
                 struct tegra_vgpu_reg_ops_params reg_ops;
                 struct tegra_vgpu_channel_priority_params channel_priority;
+                struct tegra_vgpu_channel_runlist_interleave_params channel_interleave;
                 char padding[192];
         } params;
 };