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authorSagar Kamble <skamble@nvidia.com>2020-11-08 11:46:44 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2020-11-23 11:40:17 -0500
commit7bf2833f340f87ea643d3ef66b0e4c22ffb1e891 (patch)
tree34702f0819778cc151b060e4abd88db119911cd5
parent8cb168632bef46e98da7ff5d16b03e03ddfd3d4e (diff)
gpu: nvgpu: do tsg unbind hw state check only for multi-channel TSG
Host scheduler might be confused if more than one channels are present in TSG and one of the unbound channel has NEXT set. This is not so much of an issue if there is single channel in the TSG. So don't fail unbind in that case. ctx_reload and engine_faulted check can also be skipped for single channel TSG. Bug 3144960 Change-Id: I85eb9025ea53706ce8fda6d9b4bcf6a15a300d17 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2442970 (cherry picked from commit ad4624aae3f109fc3c8c03653cb691e09f086930) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2445445 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c23
1 files changed, 22 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 4d62d8e9..072f1777 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2212,6 +2212,22 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch)
2212 return 0; 2212 return 0;
2213} 2213}
2214 2214
2215static bool gk20a_fifo_tsg_is_multi_channel(struct tsg_gk20a *tsg)
2216{
2217 bool ret = false;
2218
2219 nvgpu_rwsem_down_read(&tsg->ch_list_lock);
2220 if (nvgpu_list_first_entry(&tsg->ch_list, channel_gk20a,
2221 ch_entry) !=
2222 nvgpu_list_last_entry(&tsg->ch_list, channel_gk20a,
2223 ch_entry)) {
2224 ret = true;
2225 }
2226 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
2227
2228 return ret;
2229}
2230
2215int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) 2231int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch)
2216{ 2232{
2217 struct gk20a *g = ch->g; 2233 struct gk20a *g = ch->g;
@@ -2237,7 +2253,12 @@ int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch)
2237 goto fail_enable_tsg; 2253 goto fail_enable_tsg;
2238 } 2254 }
2239 2255
2240 if (g->ops.fifo.tsg_verify_channel_status && !tsg_timedout) { 2256 /*
2257 * State validation is only necessary if there are multiple channels in
2258 * the TSG.
2259 */
2260 if (gk20a_fifo_tsg_is_multi_channel(tsg) &&
2261 g->ops.fifo.tsg_verify_channel_status && !tsg_timedout) {
2241 err = g->ops.fifo.tsg_verify_channel_status(ch); 2262 err = g->ops.fifo.tsg_verify_channel_status(ch);
2242 if (err) { 2263 if (err) {
2243 goto fail_enable_tsg; 2264 goto fail_enable_tsg;