gpu: nvgpu: enable platform atomic feature

Support following changes related to platform atomic feature
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ

In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege,
so atomic mode register bits cannot be updated from kernel code.

atomic capability and atomic_sys_ncoh_mode bits are copied from
fb mmu_ctrl to gpcs_mmu_ctrl register.

new tu104 hal for fb_enable_nvlink function.

bug 200580236

Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013481
(cherry picked from commit 251e3eaa8029c4ae07b2cde7af5d9775e1cd8ec1)
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2274932
GVS: Gerrit_Virtual_Submit
Tested-by: Sreeniketh H <sh@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 97 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
index b98d1c41..49e8f385 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11B FB
  *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -62,6 +62,34 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
         }
 }
 
+static void gv11b_fb_set_atomic_mode(struct gk20a *g)
+{
+        u32 reg_val;
+
+        /*
+         * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
+         * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
+         */
+        reg_val = nvgpu_readl(g, fb_mmu_ctrl_r());
+        reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_mode_m(),
+                fb_mmu_ctrl_atomic_capability_mode_rmw_f());
+        reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(),
+                fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f());
+        nvgpu_writel(g, fb_mmu_ctrl_r(), reg_val);
+
+        /* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW */
+        reg_val = nvgpu_readl(g, fb_hshub_num_active_ltcs_r());
+        reg_val = set_field(reg_val, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(),
+                    fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
+        nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), reg_val);
+
+        nvgpu_log(g,  gpu_dbg_info, "fb_mmu_ctrl_r 0x%x",
+                                        gk20a_readl(g, fb_mmu_ctrl_r()));
+
+        nvgpu_log(g,   gpu_dbg_info, "fb_hshub_num_active_ltcs_r 0x%x",
+                        gk20a_readl(g, fb_hshub_num_active_ltcs_r()));
+}
+
 void gv11b_fb_init_hw(struct gk20a *g)
 {
         gm20b_fb_init_hw(g);
@@ -75,6 +103,8 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
 
         gv11b_init_nvlink_soc_credits(g);
 
+        gv11b_fb_set_atomic_mode(g);
+
         nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x",
                         gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
 
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 9506db3a..1dfecfc1 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11b GPU GR
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -4297,7 +4297,9 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
                 gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
                 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
                 gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
-                gr_gpcs_pri_mmu_ctrl_mmu_disable_m();
+                gr_gpcs_pri_mmu_ctrl_mmu_disable_m()|
+                gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m()|
+                gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m();
         gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
         gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
         gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
index 86bdaf28..fe35bb71 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -60,6 +60,22 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {
         return 0x00100800U;
 }
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void)
+{
+        return U32(0x1U) << 25U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void)
+{
+        return U32(0x1U) << 26U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void)
+{
+        return 0x0U;
+}
 static inline u32 fb_mmu_ctrl_r(void)
 {
         return 0x00100c80U;
@@ -76,6 +92,42 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
 {
         return (r >> 16U) & 0xffU;
 }
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void)
+{
+        return U32(0x3U) << 24U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
+{
+        return U32(0x1U) << 27U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_hshub_num_active_ltcs_r(void)
+{
+        return 0x001fbc20U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void)
+{
+        return U32(0x1U) << 25U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
+{
+        return 0x2000000U;
+}
 static inline u32 fb_priv_mmu_phy_secure_r(void)
 {
         return 0x00100ce4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 36a7ebf5..01dc99d5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -4976,6 +4976,14 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
 {
         return 0x1U << 31U;
 }
+static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void)
+{
+        return U32(0x3U) << 24U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
+{
+        return U32(0x1U) << 27U;
+}
 static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
 {
         return 0x00418890U;