nvgpu: common: MISRA Rule 21.2 header guard fixes

MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in common directory
by renaming them to follow the convention,
'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition
between file name and directory or 'NVGPU_HEADER-NAME' when there
is repetition.

JIRA NVGPU-1028

Change-Id: Idf10f6b179cfd96bfb8ab8e9e2bf79c26591905d
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809086
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

10 files changed, 34 insertions, 34 deletions

diff --git a/drivers/gpu/nvgpu/common/fb/fb_gp10b.h b/drivers/gpu/nvgpu/common/fb/fb_gp10b.h
index 52aa2a75..3012cb20 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gp10b.h
+++ b/drivers/gpu/nvgpu/common/fb/fb_gp10b.h
@@ -1,7 +1,7 @@
 /*
  * GP10B FB
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,11 +22,11 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GP10B_FB
-#define _NVGPU_GP10B_FB
+#ifndef NVGPU_FB_GP10B_H
+#define NVGPU_FB_GP10B_H
 struct gk20a;
 
 unsigned int gp10b_fb_compression_page_size(struct gk20a *g);
 unsigned int gp10b_fb_compressible_page_size(struct gk20a *g);
 
-#endif
+#endif /* NVGPU_FB_GP10B_H */
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.h b/drivers/gpu/nvgpu/common/fb/fb_gv100.h
index d47fded2..161d4cd7 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv100.h
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.h
@@ -1,7 +1,7 @@
 /*
  * GV100 FB
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GV100_FB
-#define _NVGPU_GV100_FB
+#ifndef NVGPU_FB_GV100_H
+#define NVGPU_FB_GV100_H
 
 struct gk20a;
 
@@ -35,4 +35,4 @@ int gv100_fb_init_nvlink(struct gk20a *g);
 int gv100_fb_enable_nvlink(struct gk20a *g);
 size_t gv100_fb_get_vidmem_size(struct gk20a *g);
 
-#endif
+#endif /* NVGPU_FB_GV100_H */
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.h b/drivers/gpu/nvgpu/common/fb/fb_gv11b.h
index 71fb3a41..66bf8e2c 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.h
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.h
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GV11B_FB
-#define _NVGPU_GV11B_FB
+#ifndef NVGPU_FB_GV11B_H
+#define NVGPU_FB_GV11B_H
 
 #define NONREPLAY_REG_INDEX             0
 #define REPLAY_REG_INDEX                1
@@ -79,4 +79,4 @@ void fb_gv11b_write_mmu_fault_status(struct gk20a *g, u32 reg_val);
 int gv11b_fb_mmu_invalidate_replay(struct gk20a *g,
                          u32 invalidate_replay_val);
 
-#endif
+#endif /* NVGPU_FB_GV11B_H */
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
index b22499ad..a543a1e5 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B FUSE
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GM20B_FUSE
-#define _NVGPU_GM20B_FUSE
+#ifndef NVGPU_FUSE_GM20B_H
+#define NVGPU_FUSE_GM20B_H
 
 #define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK       ((u32)(1 << 0))
 #define GCPLEX_CONFIG_VPR_ENABLED_MASK                  ((u32)(1 << 1))
@@ -42,4 +42,4 @@ void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
 u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g);
 u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g);
 
-#endif
+#endif /* NVGPU_FUSE_GM20B_H */
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
index f014ee8c..24be7982 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
@@ -1,7 +1,7 @@
 /*
  * GP106 FUSE
  *
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GP106_FUSE
-#define _NVGPU_GP106_FUSE
+#ifndef NVGPU_FUSE_GP106_H
+#define NVGPU_FUSE_GP106_H
 
 struct gk20a;
 
@@ -36,4 +36,4 @@ u32 gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
                                              u32 vin_id, s8 *gain,
                                              s8 *offset);
 
-#endif
+#endif /* NVGPU_FUSE_GP106_H */
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h
index d9037e22..4d3b2b07 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GP10B_FUSE
-#define _NVGPU_GP10B_FUSE
+#ifndef NVGPU_FUSE_GP10B_H
+#define NVGPU_FUSE_GP10B_H
 
 struct gk20a;
 
@@ -31,4 +31,4 @@ int gp10b_fuse_check_priv_security(struct gk20a *g);
 bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g);
 bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g);
 
-#endif
+#endif /* NVGPU_FUSE_GP10B_H */
diff --git a/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h b/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
index 7a22f030..794922d7 100644
--- a/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
+++ b/drivers/gpu/nvgpu/common/mm/buddy_allocator_priv.h
@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef BUDDY_ALLOCATOR_PRIV_H
-#define BUDDY_ALLOCATOR_PRIV_H
+#ifndef NVGPU_MM_BUDDY_ALLOCATOR_PRIV_H
+#define NVGPU_MM_BUDDY_ALLOCATOR_PRIV_H
 
 #include <nvgpu/rbtree.h>
 #include <nvgpu/list.h>
@@ -221,4 +221,4 @@ static inline struct nvgpu_allocator *balloc_owner(
         return a->owner;
 }
 
-#endif
+#endif /* NVGPU_MM_BUDDY_ALLOCATOR_PRIV_H */
diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h
index 02f20515..13d1a8ce 100644
--- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h
+++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h
@@ -19,8 +19,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __PRIV_RING_GM20B_H__
-#define __PRIV_RING_GM20B_H__
+#ifndef NVGPU_PRIV_RING_GM20B_H
+#define NVGPU_PRIV_RING_GM20B_H
 
 struct gk20a;
 
@@ -29,4 +29,4 @@ void gm20b_priv_ring_enable(struct gk20a *g);
 void gm20b_priv_set_timeout_settings(struct gk20a *g);
 u32 gm20b_priv_ring_enum_ltc(struct gk20a *g);
 
-#endif /*__PRIV_RING_GM20B_H__*/
+#endif /* NVGPU_PRIV_RING_GM20B_H */
diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h
index dd418e5b..db96ec04 100644
--- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h
+++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h
@@ -21,8 +21,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __PRIV_RING_GP10B_H__
-#define __PRIV_RING_GP10B_H__
+#ifndef NVGPU_PRIV_RING_GP10B_H
+#define NVGPU_PRIV_RING_GP10B_H
 
 struct gk20a;
 
@@ -30,4 +30,4 @@ void gp10b_priv_ring_isr(struct gk20a *g);
 void gp10b_priv_ring_decode_error_code(struct gk20a *g,
                         u32 error_code);
 
-#endif /*__PRIV_RING_GP10B_H__*/
+#endif /* NVGPU_PRIV_RING_GP10B_H */
diff --git a/drivers/gpu/nvgpu/common/xve/xve_gp106.h b/drivers/gpu/nvgpu/common/xve/xve_gp106.h
index e0be35ac..992f0c86 100644
--- a/drivers/gpu/nvgpu/common/xve/xve_gp106.h
+++ b/drivers/gpu/nvgpu/common/xve/xve_gp106.h
@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef __XVE_GP106_H__
-#define __XVE_GP106_H__
+#ifndef NVGPU_XVE_GP106_H
+#define NVGPU_XVE_GP106_H
 
 #include "gk20a/gk20a.h"
 
@@ -69,4 +69,4 @@ void xve_rearm_msi_gp106(struct gk20a *g);
 void xve_enable_shadow_rom_gp106(struct gk20a *g);
 void xve_disable_shadow_rom_gp106(struct gk20a *g);
 
-#endif
+#endif /* NVGPU_XVE_GP106_H */