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authorMahantesh Kumbar <mkumbar@nvidia.com>2018-09-14 00:07:51 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-24 11:11:44 -0400
commit7465926ccdcdad87c22c788fe04fc11961df53ba (patch)
tree9f1ce234cd0319c07a135974e2126484b3c67d81
parenta4065effdca2d16a870d05f1bf8715267635d401 (diff)
gpu:nvgpu: PMU cleanup for ACR
- Removed ACR support code from PMU module - Deleted ACR related ops from pmu ops - Deleted assigning of ACR related ops using pmu ops during HAL init -Removed code related to ACR bootstrap & dependent code for all chips. JIRA NVGPU-1147 Change-Id: I47a851a6b67a9aacde863685537c34566f97dc8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817990 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat
-rw-r--r--drivers/gpu/nvgpu/common/pmu/pmu_fw.c11
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.c355
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.h5
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c8
-rw-r--r--drivers/gpu/nvgpu/gp106/acr_gp106.c132
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c7
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c9
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c7
-rw-r--r--drivers/gpu/nvgpu/gv11b/acr_gv11b.c206
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c9
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gk20a.h6
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c9
12 files changed, 0 insertions, 764 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index c2d6a921..c1416493 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -1648,17 +1648,6 @@ static void nvgpu_remove_pmu_support(struct nvgpu_pmu *pmu)
1648 nvgpu_release_firmware(g, g->acr.pmu_desc); 1648 nvgpu_release_firmware(g, g->acr.pmu_desc);
1649 } 1649 }
1650 1650
1651 if (g->acr.acr_fw) {
1652 nvgpu_release_firmware(g, g->acr.acr_fw);
1653 }
1654
1655 if (g->acr.hsbl_fw) {
1656 nvgpu_release_firmware(g, g->acr.hsbl_fw);
1657 }
1658
1659 nvgpu_dma_unmap_free(vm, &g->acr.acr_ucode);
1660 nvgpu_dma_unmap_free(vm, &g->acr.hsbl_ucode);
1661
1662 nvgpu_dma_unmap_free(vm, &pmu->seq_buf); 1651 nvgpu_dma_unmap_free(vm, &pmu->seq_buf);
1663 1652
1664 nvgpu_dma_unmap_free(vm, &pmu->super_surface_buf); 1653 nvgpu_dma_unmap_free(vm, &pmu->super_surface_buf);
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index be05a8a8..87f3ef54 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -70,18 +70,6 @@ static get_ucode_details pmu_acr_supp_ucode_list[] = {
70 gpccs_ucode_details, 70 gpccs_ucode_details,
71}; 71};
72 72
73/*Once is LS mode, cpuctl_alias is only accessible*/
74static void start_gm20b_pmu(struct gk20a *g)
75{
76 /*disable irqs for hs falcon booting as we will poll for halt*/
77 nvgpu_mutex_acquire(&g->pmu.isr_mutex);
78 g->ops.pmu.pmu_enable_irq(&g->pmu, true);
79 g->pmu.isr_enabled = true;
80 nvgpu_mutex_release(&g->pmu.isr_mutex);
81 gk20a_writel(g, pwr_falcon_cpuctl_alias_r(),
82 pwr_falcon_cpuctl_startcpu_f(1));
83}
84
85void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) 73void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
86{ 74{
87 g->ops.fb.read_wpr_info(g, inf); 75 g->ops.fb.read_wpr_info(g, inf);
@@ -1024,123 +1012,6 @@ static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm)
1024 return 0; 1012 return 0;
1025} 1013}
1026 1014
1027/*Loads ACR bin to FB mem and bootstraps PMU with bootloader code
1028 * start and end are addresses of ucode blob in non-WPR region*/
1029int gm20b_bootstrap_hs_flcn(struct gk20a *g)
1030{
1031 struct mm_gk20a *mm = &g->mm;
1032 struct vm_gk20a *vm = mm->pmu.vm;
1033 int err = 0;
1034 u64 *acr_dmem;
1035 u32 img_size_in_bytes = 0;
1036 u32 status, size;
1037 u64 start;
1038 struct acr_desc *acr = &g->acr;
1039 struct nvgpu_firmware *acr_fw = acr->acr_fw;
1040 struct flcn_bl_dmem_desc *bl_dmem_desc = &acr->bl_dmem_desc;
1041 u32 *acr_ucode_header_t210_load;
1042 u32 *acr_ucode_data_t210_load;
1043
1044 start = nvgpu_mem_get_addr(g, &acr->ucode_blob);
1045 size = acr->ucode_blob.size;
1046
1047 nvgpu_pmu_dbg(g, " ");
1048
1049 if (!acr_fw) {
1050 /*First time init case*/
1051 acr_fw = nvgpu_request_firmware(g, GM20B_HSBIN_PMU_UCODE_IMAGE, 0);
1052 if (!acr_fw) {
1053 nvgpu_err(g, "pmu ucode get fail");
1054 return -ENOENT;
1055 }
1056 acr->acr_fw = acr_fw;
1057 acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data;
1058 acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data +
1059 acr->hsbin_hdr->header_offset);
1060 acr_ucode_data_t210_load = (u32 *)(acr_fw->data +
1061 acr->hsbin_hdr->data_offset);
1062 acr_ucode_header_t210_load = (u32 *)(acr_fw->data +
1063 acr->fw_hdr->hdr_offset);
1064 img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256);
1065
1066 /* Lets patch the signatures first.. */
1067 if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load,
1068 (u32 *)(acr_fw->data +
1069 acr->fw_hdr->sig_prod_offset),
1070 (u32 *)(acr_fw->data +
1071 acr->fw_hdr->sig_dbg_offset),
1072 (u32 *)(acr_fw->data +
1073 acr->fw_hdr->patch_loc),
1074 (u32 *)(acr_fw->data +
1075 acr->fw_hdr->patch_sig)) < 0) {
1076 nvgpu_err(g, "patch signatures fail");
1077 err = -1;
1078 goto err_release_acr_fw;
1079 }
1080 err = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes,
1081 &acr->acr_ucode);
1082 if (err) {
1083 err = -ENOMEM;
1084 goto err_release_acr_fw;
1085 }
1086
1087 acr_dmem = (u64 *)
1088 &(((u8 *)acr_ucode_data_t210_load)[
1089 acr_ucode_header_t210_load[2]]);
1090 acr->acr_dmem_desc = (struct flcn_acr_desc *)((u8 *)(
1091 acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]);
1092 ((struct flcn_acr_desc *)acr_dmem)->nonwpr_ucode_blob_start =
1093 start;
1094 ((struct flcn_acr_desc *)acr_dmem)->nonwpr_ucode_blob_size =
1095 size;
1096 ((struct flcn_acr_desc *)acr_dmem)->regions.no_regions = 2;
1097 ((struct flcn_acr_desc *)acr_dmem)->wpr_offset = 0;
1098
1099 nvgpu_mem_wr_n(g, &acr->acr_ucode, 0,
1100 acr_ucode_data_t210_load, img_size_in_bytes);
1101 /*
1102 * In order to execute this binary, we will be using
1103 * a bootloader which will load this image into PMU IMEM/DMEM.
1104 * Fill up the bootloader descriptor for PMU HAL to use..
1105 * TODO: Use standard descriptor which the generic bootloader is
1106 * checked in.
1107 */
1108
1109 bl_dmem_desc->signature[0] = 0;
1110 bl_dmem_desc->signature[1] = 0;
1111 bl_dmem_desc->signature[2] = 0;
1112 bl_dmem_desc->signature[3] = 0;
1113 bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
1114 bl_dmem_desc->code_dma_base =
1115 (unsigned int)(((u64)acr->acr_ucode.gpu_va >> 8));
1116 bl_dmem_desc->code_dma_base1 = 0x0;
1117 bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0];
1118 bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1];
1119 bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5];
1120 bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6];
1121 bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */
1122 bl_dmem_desc->data_dma_base =
1123 bl_dmem_desc->code_dma_base +
1124 ((acr_ucode_header_t210_load[2]) >> 8);
1125 bl_dmem_desc->data_dma_base1 = 0x0;
1126 bl_dmem_desc->data_size = acr_ucode_header_t210_load[3];
1127 } else {
1128 acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0;
1129 }
1130 status = pmu_exec_gen_bl(g, bl_dmem_desc, 1);
1131 if (status != 0) {
1132 err = status;
1133 goto err_free_ucode_map;
1134 }
1135 return 0;
1136err_free_ucode_map:
1137 nvgpu_dma_unmap_free(vm, &acr->acr_ucode);
1138err_release_acr_fw:
1139 nvgpu_release_firmware(g, acr_fw);
1140 acr->acr_fw = NULL;
1141 return err;
1142}
1143
1144/* 1015/*
1145 * @brief Patch signatures into ucode image 1016 * @brief Patch signatures into ucode image
1146 */ 1017 */
@@ -1172,33 +1043,6 @@ int acr_ucode_patch_sig(struct gk20a *g,
1172 return 0; 1043 return 0;
1173} 1044}
1174 1045
1175static int bl_bootstrap(struct nvgpu_pmu *pmu,
1176 struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz)
1177{
1178 struct gk20a *g = gk20a_from_pmu(pmu);
1179 struct mm_gk20a *mm = &g->mm;
1180 struct nvgpu_falcon_bl_info bl_info;
1181
1182 nvgpu_log_fn(g, " ");
1183 gk20a_writel(g, pwr_falcon_itfen_r(),
1184 gk20a_readl(g, pwr_falcon_itfen_r()) |
1185 pwr_falcon_itfen_ctxen_enable_f());
1186 gk20a_writel(g, pwr_pmu_new_instblk_r(),
1187 pwr_pmu_new_instblk_ptr_f(
1188 nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
1189 pwr_pmu_new_instblk_valid_f(1) |
1190 pwr_pmu_new_instblk_target_sys_coh_f());
1191
1192 bl_info.bl_src = g->acr.hsbl_ucode.cpu_va;
1193 bl_info.bl_desc = (u8 *)pbl_desc;
1194 bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc);
1195 bl_info.bl_size = bl_sz;
1196 bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag;
1197 nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, &bl_info);
1198
1199 return 0;
1200}
1201
1202int gm20b_init_nspmu_setup_hw1(struct gk20a *g) 1046int gm20b_init_nspmu_setup_hw1(struct gk20a *g)
1203{ 1047{
1204 struct nvgpu_pmu *pmu = &g->pmu; 1048 struct nvgpu_pmu *pmu = &g->pmu;
@@ -1268,202 +1112,3 @@ void gm20b_update_lspmu_cmdline_args(struct gk20a *g)
1268 (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), 1112 (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
1269 g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); 1113 g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
1270} 1114}
1271
1272int gm20b_init_pmu_setup_hw1(struct gk20a *g,
1273 void *desc, u32 bl_sz)
1274{
1275
1276 struct nvgpu_pmu *pmu = &g->pmu;
1277 int err;
1278
1279 nvgpu_log_fn(g, " ");
1280
1281 nvgpu_mutex_acquire(&pmu->isr_mutex);
1282 nvgpu_flcn_reset(pmu->flcn);
1283 pmu->isr_enabled = true;
1284 nvgpu_mutex_release(&pmu->isr_mutex);
1285
1286 if (g->ops.pmu.setup_apertures) {
1287 g->ops.pmu.setup_apertures(g);
1288 }
1289 if (g->ops.pmu.update_lspmu_cmdline_args) {
1290 g->ops.pmu.update_lspmu_cmdline_args(g);
1291 }
1292
1293 /*disable irqs for hs falcon booting as we will poll for halt*/
1294 nvgpu_mutex_acquire(&pmu->isr_mutex);
1295 g->ops.pmu.pmu_enable_irq(pmu, false);
1296 pmu->isr_enabled = false;
1297 nvgpu_mutex_release(&pmu->isr_mutex);
1298 /*Clearing mailbox register used to reflect capabilities*/
1299 gk20a_writel(g, pwr_falcon_mailbox1_r(), 0);
1300 err = bl_bootstrap(pmu, desc, bl_sz);
1301 if (err) {
1302 return err;
1303 }
1304 return 0;
1305}
1306
1307/*
1308* Executes a generic bootloader and wait for PMU to halt.
1309* This BL will be used for those binaries that are loaded
1310* and executed at times other than RM PMU Binary execution.
1311*
1312* @param[in] g gk20a pointer
1313* @param[in] desc Bootloader descriptor
1314* @param[in] dma_idx DMA Index
1315* @param[in] b_wait_for_halt Wait for PMU to HALT
1316*/
1317int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt)
1318{
1319 struct mm_gk20a *mm = &g->mm;
1320 struct vm_gk20a *vm = mm->pmu.vm;
1321 int err = 0;
1322 u32 bl_sz;
1323 struct acr_desc *acr = &g->acr;
1324 struct nvgpu_firmware *hsbl_fw = acr->hsbl_fw;
1325 struct hsflcn_bl_desc *pmu_bl_gm10x_desc;
1326 u32 *pmu_bl_gm10x = NULL;
1327 nvgpu_pmu_dbg(g, " ");
1328
1329 if (!hsbl_fw) {
1330 hsbl_fw = nvgpu_request_firmware(g,
1331 GM20B_HSBIN_PMU_BL_UCODE_IMAGE, 0);
1332 if (!hsbl_fw) {
1333 nvgpu_err(g, "pmu ucode load fail");
1334 return -ENOENT;
1335 }
1336 acr->hsbl_fw = hsbl_fw;
1337 acr->bl_bin_hdr = (struct bin_hdr *)hsbl_fw->data;
1338 acr->pmu_hsbl_desc = (struct hsflcn_bl_desc *)(hsbl_fw->data +
1339 acr->bl_bin_hdr->header_offset);
1340 pmu_bl_gm10x_desc = acr->pmu_hsbl_desc;
1341 pmu_bl_gm10x = (u32 *)(hsbl_fw->data +
1342 acr->bl_bin_hdr->data_offset);
1343 bl_sz = ALIGN(pmu_bl_gm10x_desc->bl_img_hdr.bl_code_size,
1344 256);
1345 acr->hsbl_ucode.size = bl_sz;
1346 nvgpu_pmu_dbg(g, "Executing Generic Bootloader\n");
1347
1348 /*TODO in code verify that enable PMU is done,
1349 scrubbing etc is done*/
1350 /*TODO in code verify that gmmu vm init is done*/
1351 err = nvgpu_dma_alloc_sys(g, bl_sz, &acr->hsbl_ucode);
1352 if (err) {
1353 nvgpu_err(g, "failed to allocate memory");
1354 goto err_done;
1355 }
1356
1357 acr->hsbl_ucode.gpu_va = nvgpu_gmmu_map(vm,
1358 &acr->hsbl_ucode,
1359 bl_sz,
1360 0, /* flags */
1361 gk20a_mem_flag_read_only, false,
1362 acr->hsbl_ucode.aperture);
1363 if (!acr->hsbl_ucode.gpu_va) {
1364 nvgpu_err(g, "failed to map pmu ucode memory!!");
1365 goto err_free_ucode;
1366 }
1367
1368 nvgpu_mem_wr_n(g, &acr->hsbl_ucode, 0, pmu_bl_gm10x, bl_sz);
1369 nvgpu_pmu_dbg(g, "Copied bl ucode to bl_cpuva\n");
1370 }
1371 /*
1372 * Disable interrupts to avoid kernel hitting breakpoint due
1373 * to PMU halt
1374 */
1375
1376 if (g->ops.pmu.falcon_clear_halt_interrupt_status(g,
1377 gk20a_get_gr_idle_timeout(g))) {
1378 goto err_unmap_bl;
1379 }
1380
1381 nvgpu_pmu_dbg(g, "phys sec reg %x\n", gk20a_readl(g,
1382 pwr_falcon_mmu_phys_sec_r()));
1383 nvgpu_pmu_dbg(g, "sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r()));
1384
1385 g->ops.pmu.init_falcon_setup_hw(g, desc, acr->hsbl_ucode.size);
1386
1387 /* Poll for HALT */
1388 if (b_wait_for_halt) {
1389 err = g->ops.pmu.falcon_wait_for_halt(g,
1390 ACR_COMPLETION_TIMEOUT_MS);
1391 if (err == 0) {
1392 /* Clear the HALT interrupt */
1393 if (g->ops.pmu.falcon_clear_halt_interrupt_status(g,
1394 gk20a_get_gr_idle_timeout(g))) {
1395 goto err_unmap_bl;
1396 }
1397 } else {
1398 goto err_unmap_bl;
1399 }
1400 }
1401 nvgpu_pmu_dbg(g, "after waiting for halt, err %x\n", err);
1402 nvgpu_pmu_dbg(g, "phys sec reg %x\n", gk20a_readl(g,
1403 pwr_falcon_mmu_phys_sec_r()));
1404 nvgpu_pmu_dbg(g, "sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r()));
1405 start_gm20b_pmu(g);
1406 return 0;
1407err_unmap_bl:
1408 nvgpu_gmmu_unmap(vm, &acr->hsbl_ucode, acr->hsbl_ucode.gpu_va);
1409err_free_ucode:
1410 nvgpu_dma_free(g, &acr->hsbl_ucode);
1411err_done:
1412 nvgpu_release_firmware(g, hsbl_fw);
1413 return err;
1414}
1415
1416/*!
1417* Wait for PMU to halt
1418* @param[in] g GPU object pointer
1419* @param[in] timeout_ms Timeout in msec for PMU to halt
1420* @return '0' if PMU halts
1421*/
1422int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms)
1423{
1424 struct nvgpu_pmu *pmu = &g->pmu;
1425 u32 data = 0;
1426 int ret = 0;
1427
1428 ret = nvgpu_flcn_wait_for_halt(pmu->flcn, timeout_ms);
1429 if (ret) {
1430 nvgpu_err(g, "ACR boot timed out");
1431 goto exit;
1432 }
1433
1434 g->acr.capabilities = gk20a_readl(g, pwr_falcon_mailbox1_r());
1435 nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities);
1436 data = gk20a_readl(g, pwr_falcon_mailbox0_r());
1437 if (data) {
1438 nvgpu_err(g, "ACR boot failed, err %x", data);
1439 ret = -EAGAIN;
1440 goto exit;
1441 }
1442
1443exit:
1444 if (ret) {
1445 nvgpu_kill_task_pg_init(g);
1446 nvgpu_pmu_state_change(g, PMU_STATE_OFF, false);
1447 nvgpu_flcn_dump_stats(pmu->flcn);
1448 }
1449
1450 return ret;
1451}
1452
1453/*!
1454* Wait for PMU halt interrupt status to be cleared
1455* @param[in] g GPU object pointer
1456* @param[in] timeout_ms Timeout in msec for halt to clear
1457* @return '0' if PMU halt irq status is clear
1458*/
1459int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout_ms)
1460{
1461 struct nvgpu_pmu *pmu = &g->pmu;
1462 int status = 0;
1463
1464 if (nvgpu_flcn_clear_halt_intr_status(pmu->flcn, timeout_ms)) {
1465 status = -EBUSY;
1466 }
1467
1468 return status;
1469}
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index 7c9743ab..329d53b8 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -35,7 +35,6 @@
35 35
36bool gm20b_is_pmu_supported(struct gk20a *g); 36bool gm20b_is_pmu_supported(struct gk20a *g);
37int prepare_ucode_blob(struct gk20a *g); 37int prepare_ucode_blob(struct gk20a *g);
38int gm20b_bootstrap_hs_flcn(struct gk20a *g);
39bool gm20b_is_lazy_bootstrap(u32 falcon_id); 38bool gm20b_is_lazy_bootstrap(u32 falcon_id);
40bool gm20b_is_priv_load(u32 falcon_id); 39bool gm20b_is_priv_load(u32 falcon_id);
41void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); 40void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
@@ -44,14 +43,10 @@ int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
44 void *lsfm, u32 *p_bl_gen_desc_size); 43 void *lsfm, u32 *p_bl_gen_desc_size);
45int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, 44int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
46 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); 45 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
47int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms);
48int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
49int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz);
50void gm20b_update_lspmu_cmdline_args(struct gk20a *g); 46void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
51void gm20b_setup_apertures(struct gk20a *g); 47void gm20b_setup_apertures(struct gk20a *g);
52 48
53int gm20b_pmu_setup_sw(struct gk20a *g); 49int gm20b_pmu_setup_sw(struct gk20a *g);
54int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt);
55int gm20b_init_nspmu_setup_hw1(struct gk20a *g); 50int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
56int acr_ucode_patch_sig(struct gk20a *g, 51int acr_ucode_patch_sig(struct gk20a *g,
57 unsigned int *p_img, 52 unsigned int *p_img,
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 114d259a..39c902d7 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -722,19 +722,12 @@ int gm20b_init_hal(struct gk20a *g)
722 /* Add in ops from gm20b acr */ 722 /* Add in ops from gm20b acr */
723 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported; 723 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
724 gops->pmu.prepare_ucode = prepare_ucode_blob; 724 gops->pmu.prepare_ucode = prepare_ucode_blob;
725 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
726 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap; 725 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
727 gops->pmu.is_priv_load = gm20b_is_priv_load; 726 gops->pmu.is_priv_load = gm20b_is_priv_load;
728 gops->pmu.get_wpr = gm20b_wpr_info;
729 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
730 gops->pmu.pmu_populate_loader_cfg = 727 gops->pmu.pmu_populate_loader_cfg =
731 gm20b_pmu_populate_loader_cfg; 728 gm20b_pmu_populate_loader_cfg;
732 gops->pmu.flcn_populate_bl_dmem_desc = 729 gops->pmu.flcn_populate_bl_dmem_desc =
733 gm20b_flcn_populate_bl_dmem_desc; 730 gm20b_flcn_populate_bl_dmem_desc;
734 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
735 gops->pmu.falcon_clear_halt_interrupt_status =
736 clear_halt_interrupt_status;
737 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
738 gops->pmu.update_lspmu_cmdline_args = 731 gops->pmu.update_lspmu_cmdline_args =
739 gm20b_update_lspmu_cmdline_args; 732 gm20b_update_lspmu_cmdline_args;
740 gops->pmu.setup_apertures = gm20b_setup_apertures; 733 gops->pmu.setup_apertures = gm20b_setup_apertures;
@@ -747,7 +740,6 @@ int gm20b_init_hal(struct gk20a *g)
747 /* Inherit from gk20a */ 740 /* Inherit from gk20a */
748 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; 741 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
749 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob; 742 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
750 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
751 gops->pmu.pmu_nsbootstrap = pmu_bootstrap; 743 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
752 744
753 gops->pmu.load_lsfalcon_ucode = NULL; 745 gops->pmu.load_lsfalcon_ucode = NULL;
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 9b8558db..7bb099e5 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -1191,135 +1191,3 @@ int lsf_gen_wpr_requirements(struct gk20a *g,
1191 plsfm->wpr_size = wpr_offset; 1191 plsfm->wpr_size = wpr_offset;
1192 return 0; 1192 return 0;
1193} 1193}
1194
1195/*Loads ACR bin to FB mem and bootstraps PMU with bootloader code
1196 * start and end are addresses of ucode blob in non-WPR region*/
1197int gp106_bootstrap_hs_flcn(struct gk20a *g)
1198{
1199 struct mm_gk20a *mm = &g->mm;
1200 struct vm_gk20a *vm = mm->pmu.vm;
1201 int err = 0;
1202 u64 *acr_dmem;
1203 u32 img_size_in_bytes = 0;
1204 u32 status;
1205 struct acr_desc *acr = &g->acr;
1206 struct nvgpu_firmware *acr_fw = acr->acr_fw;
1207 struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1;
1208 u32 *acr_ucode_header_t210_load;
1209 u32 *acr_ucode_data_t210_load;
1210 struct wpr_carveout_info wpr_inf;
1211
1212 gp106_dbg_pmu(g, " ");
1213
1214 if (!acr_fw) {
1215 /*First time init case*/
1216 acr_fw = nvgpu_request_firmware(g,
1217 GM20B_HSBIN_PMU_UCODE_IMAGE,
1218 NVGPU_REQUEST_FIRMWARE_NO_SOC);
1219 if (!acr_fw) {
1220 nvgpu_err(g, "pmu ucode get fail");
1221 return -ENOENT;
1222 }
1223 acr->acr_fw = acr_fw;
1224 acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data;
1225 acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data +
1226 acr->hsbin_hdr->header_offset);
1227 acr_ucode_data_t210_load = (u32 *)(acr_fw->data +
1228 acr->hsbin_hdr->data_offset);
1229 acr_ucode_header_t210_load = (u32 *)(acr_fw->data +
1230 acr->fw_hdr->hdr_offset);
1231 img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256);
1232
1233 /* Lets patch the signatures first.. */
1234 if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load,
1235 (u32 *)(acr_fw->data +
1236 acr->fw_hdr->sig_prod_offset),
1237 (u32 *)(acr_fw->data +
1238 acr->fw_hdr->sig_dbg_offset),
1239 (u32 *)(acr_fw->data +
1240 acr->fw_hdr->patch_loc),
1241 (u32 *)(acr_fw->data +
1242 acr->fw_hdr->patch_sig)) < 0) {
1243 nvgpu_err(g, "patch signatures fail");
1244 err = -1;
1245 goto err_release_acr_fw;
1246 }
1247 err = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes,
1248 &acr->acr_ucode);
1249 if (err) {
1250 err = -ENOMEM;
1251 goto err_release_acr_fw;
1252 }
1253
1254 g->ops.pmu.get_wpr(g, &wpr_inf);
1255
1256 acr_dmem = (u64 *)
1257 &(((u8 *)acr_ucode_data_t210_load)[
1258 acr_ucode_header_t210_load[2]]);
1259 acr->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)((u8 *)(
1260 acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]);
1261 ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_start =
1262 wpr_inf.nonwpr_base;
1263 ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_size =
1264 wpr_inf.size;
1265 ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.no_regions = 1;
1266 ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_offset = 0;
1267
1268 ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_region_id = 1;
1269 ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
1270 0].region_id = 1;
1271 ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
1272 0].start_addr = (wpr_inf.wpr_base ) >> 8;
1273 ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
1274 0].end_addr = ((wpr_inf.wpr_base) + wpr_inf.size) >> 8;
1275 ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[
1276 0].shadowmMem_startaddress = wpr_inf.nonwpr_base >> 8;
1277
1278 nvgpu_mem_wr_n(g, &acr->acr_ucode, 0,
1279 acr_ucode_data_t210_load, img_size_in_bytes);
1280
1281 /*
1282 * In order to execute this binary, we will be using
1283 * a bootloader which will load this image into PMU IMEM/DMEM.
1284 * Fill up the bootloader descriptor for PMU HAL to use..
1285 * TODO: Use standard descriptor which the generic bootloader is
1286 * checked in.
1287 */
1288
1289 bl_dmem_desc->signature[0] = 0;
1290 bl_dmem_desc->signature[1] = 0;
1291 bl_dmem_desc->signature[2] = 0;
1292 bl_dmem_desc->signature[3] = 0;
1293 bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
1294 flcn64_set_dma( &bl_dmem_desc->code_dma_base,
1295 acr->acr_ucode.gpu_va);
1296 bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0];
1297 bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1];
1298 bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5];
1299 bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6];
1300 bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */
1301 flcn64_set_dma( &bl_dmem_desc->data_dma_base,
1302 acr->acr_ucode.gpu_va +
1303 (acr_ucode_header_t210_load[2]));
1304 bl_dmem_desc->data_size = acr_ucode_header_t210_load[3];
1305 } else {
1306 acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0;
1307 }
1308
1309 status = pmu_exec_gen_bl(g, bl_dmem_desc, 1);
1310 if (status != 0) {
1311 err = status;
1312 goto err_free_ucode_map;
1313 }
1314
1315 /* sec2 reset - to keep it idle */
1316 nvgpu_flcn_reset(&g->sec2_flcn);
1317
1318 return 0;
1319err_free_ucode_map:
1320 nvgpu_dma_unmap_free(vm, &acr->acr_ucode);
1321err_release_acr_fw:
1322 nvgpu_release_firmware(g, acr_fw);
1323 acr->acr_fw = NULL;
1324 return err;
1325}
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 94669eb3..e94bc1ea 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -618,15 +618,8 @@ static const struct gpu_ops gp106_ops = {
618 .is_lazy_bootstrap = gp106_is_lazy_bootstrap, 618 .is_lazy_bootstrap = gp106_is_lazy_bootstrap,
619 .is_priv_load = gp106_is_priv_load, 619 .is_priv_load = gp106_is_priv_load,
620 .prepare_ucode = gp106_prepare_ucode_blob, 620 .prepare_ucode = gp106_prepare_ucode_blob,
621 .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn,
622 .get_wpr = gp106_wpr_info,
623 .alloc_blob_space = gp106_alloc_blob_space,
624 .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, 621 .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg,
625 .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, 622 .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc,
626 .falcon_wait_for_halt = gp106_sec2_wait_for_halt,
627 .falcon_clear_halt_interrupt_status =
628 gp106_sec2_clear_halt_interrupt_status,
629 .init_falcon_setup_hw = init_sec2_setup_hw1,
630 .pmu_queue_tail = gk20a_pmu_queue_tail, 623 .pmu_queue_tail = gk20a_pmu_queue_tail,
631 .pmu_get_queue_head = pwr_pmu_queue_head_r, 624 .pmu_get_queue_head = pwr_pmu_queue_head_r,
632 .pmu_mutex_release = gk20a_pmu_mutex_release, 625 .pmu_mutex_release = gk20a_pmu_mutex_release,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 1f9e84d3..d8a430fa 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -782,19 +782,12 @@ int gp10b_init_hal(struct gk20a *g)
782 /* Add in ops from gm20b acr */ 782 /* Add in ops from gm20b acr */
783 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported, 783 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported,
784 gops->pmu.prepare_ucode = prepare_ucode_blob, 784 gops->pmu.prepare_ucode = prepare_ucode_blob,
785 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
786 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, 785 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
787 gops->pmu.is_priv_load = gm20b_is_priv_load, 786 gops->pmu.is_priv_load = gm20b_is_priv_load,
788 gops->pmu.get_wpr = gm20b_wpr_info,
789 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
790 gops->pmu.pmu_populate_loader_cfg = 787 gops->pmu.pmu_populate_loader_cfg =
791 gm20b_pmu_populate_loader_cfg, 788 gm20b_pmu_populate_loader_cfg,
792 gops->pmu.flcn_populate_bl_dmem_desc = 789 gops->pmu.flcn_populate_bl_dmem_desc =
793 gm20b_flcn_populate_bl_dmem_desc, 790 gm20b_flcn_populate_bl_dmem_desc,
794 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
795 gops->pmu.falcon_clear_halt_interrupt_status =
796 clear_halt_interrupt_status,
797 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
798 gops->pmu.update_lspmu_cmdline_args = 791 gops->pmu.update_lspmu_cmdline_args =
799 gm20b_update_lspmu_cmdline_args; 792 gm20b_update_lspmu_cmdline_args;
800 gops->pmu.setup_apertures = gm20b_setup_apertures; 793 gops->pmu.setup_apertures = gm20b_setup_apertures;
@@ -809,12 +802,10 @@ int gp10b_init_hal(struct gk20a *g)
809 /* Inherit from gk20a */ 802 /* Inherit from gk20a */
810 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, 803 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
811 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, 804 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
812 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
813 gops->pmu.pmu_nsbootstrap = pmu_bootstrap, 805 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
814 806
815 gops->pmu.load_lsfalcon_ucode = NULL; 807 gops->pmu.load_lsfalcon_ucode = NULL;
816 gops->pmu.init_wpr_region = NULL; 808 gops->pmu.init_wpr_region = NULL;
817 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
818 809
819 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; 810 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
820 } 811 }
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 63ab04e9..85fc1915 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -719,15 +719,8 @@ static const struct gpu_ops gv100_ops = {
719 .is_lazy_bootstrap = gp106_is_lazy_bootstrap, 719 .is_lazy_bootstrap = gp106_is_lazy_bootstrap,
720 .is_priv_load = gp106_is_priv_load, 720 .is_priv_load = gp106_is_priv_load,
721 .prepare_ucode = gp106_prepare_ucode_blob, 721 .prepare_ucode = gp106_prepare_ucode_blob,
722 .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn,
723 .get_wpr = gp106_wpr_info,
724 .alloc_blob_space = gp106_alloc_blob_space,
725 .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, 722 .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg,
726 .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, 723 .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc,
727 .falcon_wait_for_halt = gp106_sec2_wait_for_halt,
728 .falcon_clear_halt_interrupt_status =
729 gp106_sec2_clear_halt_interrupt_status,
730 .init_falcon_setup_hw = init_sec2_setup_hw1,
731 .pmu_queue_tail = gk20a_pmu_queue_tail, 724 .pmu_queue_tail = gk20a_pmu_queue_tail,
732 .pmu_get_queue_head = pwr_pmu_queue_head_r, 725 .pmu_get_queue_head = pwr_pmu_queue_head_r,
733 .pmu_mutex_release = gk20a_pmu_mutex_release, 726 .pmu_mutex_release = gk20a_pmu_mutex_release,
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
index c7b854bf..f5ca144a 100644
--- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
@@ -47,11 +47,6 @@
47#define gv11b_dbg_pmu(g, fmt, arg...) \ 47#define gv11b_dbg_pmu(g, fmt, arg...) \
48 nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) 48 nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
49 49
50static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value)
51{
52 dma_addr->lo |= u64_lo32(value);
53 dma_addr->hi |= u64_hi32(value);
54}
55/*Externs*/ 50/*Externs*/
56 51
57/*Forwards*/ 52/*Forwards*/
@@ -68,173 +63,6 @@ int gv11b_alloc_blob_space(struct gk20a *g,
68 return err; 63 return err;
69} 64}
70 65
71/*Loads ACR bin to FB mem and bootstraps PMU with bootloader code
72 * start and end are addresses of ucode blob in non-WPR region*/
73int gv11b_bootstrap_hs_flcn(struct gk20a *g)
74{
75 struct mm_gk20a *mm = &g->mm;
76 struct vm_gk20a *vm = mm->pmu.vm;
77 int err = 0;
78 u64 *acr_dmem;
79 u32 img_size_in_bytes = 0;
80 u32 status, size, index;
81 u64 start;
82 struct acr_desc *acr = &g->acr;
83 struct nvgpu_firmware *acr_fw = acr->acr_fw;
84 struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1;
85 u32 *acr_ucode_header_t210_load;
86 u32 *acr_ucode_data_t210_load;
87
88 start = nvgpu_mem_get_addr(g, &acr->ucode_blob);
89 size = acr->ucode_blob.size;
90
91 gv11b_dbg_pmu(g, "acr ucode blob start %llx\n", start);
92 gv11b_dbg_pmu(g, "acr ucode blob size %x\n", size);
93
94 gv11b_dbg_pmu(g, " ");
95
96 if (!acr_fw) {
97 /*First time init case*/
98 acr_fw = nvgpu_request_firmware(g,
99 GM20B_HSBIN_PMU_UCODE_IMAGE, 0);
100 if (!acr_fw) {
101 nvgpu_err(g, "pmu ucode get fail");
102 return -ENOENT;
103 }
104 acr->acr_fw = acr_fw;
105 acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data;
106 acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data +
107 acr->hsbin_hdr->header_offset);
108 acr_ucode_data_t210_load = (u32 *)(acr_fw->data +
109 acr->hsbin_hdr->data_offset);
110 acr_ucode_header_t210_load = (u32 *)(acr_fw->data +
111 acr->fw_hdr->hdr_offset);
112 img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256);
113
114 gv11b_dbg_pmu(g, "sig dbg offset %u\n",
115 acr->fw_hdr->sig_dbg_offset);
116 gv11b_dbg_pmu(g, "sig dbg size %u\n", acr->fw_hdr->sig_dbg_size);
117 gv11b_dbg_pmu(g, "sig prod offset %u\n",
118 acr->fw_hdr->sig_prod_offset);
119 gv11b_dbg_pmu(g, "sig prod size %u\n",
120 acr->fw_hdr->sig_prod_size);
121 gv11b_dbg_pmu(g, "patch loc %u\n", acr->fw_hdr->patch_loc);
122 gv11b_dbg_pmu(g, "patch sig %u\n", acr->fw_hdr->patch_sig);
123 gv11b_dbg_pmu(g, "header offset %u\n", acr->fw_hdr->hdr_offset);
124 gv11b_dbg_pmu(g, "header size %u\n", acr->fw_hdr->hdr_size);
125
126 /* Lets patch the signatures first.. */
127 if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load,
128 (u32 *)(acr_fw->data +
129 acr->fw_hdr->sig_prod_offset),
130 (u32 *)(acr_fw->data +
131 acr->fw_hdr->sig_dbg_offset),
132 (u32 *)(acr_fw->data +
133 acr->fw_hdr->patch_loc),
134 (u32 *)(acr_fw->data +
135 acr->fw_hdr->patch_sig)) < 0) {
136 nvgpu_err(g, "patch signatures fail");
137 err = -1;
138 goto err_release_acr_fw;
139 }
140 err = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes,
141 &acr->acr_ucode);
142 if (err) {
143 err = -ENOMEM;
144 goto err_release_acr_fw;
145 }
146
147 for (index = 0; index < 9; index++) {
148 gv11b_dbg_pmu(g, "acr_ucode_header_t210_load %u\n",
149 acr_ucode_header_t210_load[index]);
150 }
151
152 acr_dmem = (u64 *)
153 &(((u8 *)acr_ucode_data_t210_load)[
154 acr_ucode_header_t210_load[2]]);
155 acr->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)((u8 *)(
156 acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]);
157 ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_start =
158 (start);
159 ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_size =
160 size;
161 ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.no_regions = 2;
162 ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_offset = 0;
163
164 nvgpu_mem_wr_n(g, &acr->acr_ucode, 0,
165 acr_ucode_data_t210_load, img_size_in_bytes);
166 /*
167 * In order to execute this binary, we will be using
168 * a bootloader which will load this image into PMU IMEM/DMEM.
169 * Fill up the bootloader descriptor for PMU HAL to use..
170 * TODO: Use standard descriptor which the generic bootloader is
171 * checked in.
172 */
173 bl_dmem_desc->signature[0] = 0;
174 bl_dmem_desc->signature[1] = 0;
175 bl_dmem_desc->signature[2] = 0;
176 bl_dmem_desc->signature[3] = 0;
177 bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
178 flcn64_set_dma(&bl_dmem_desc->code_dma_base,
179 acr->acr_ucode.gpu_va);
180 bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0];
181 bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1];
182 bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5];
183 bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6];
184 bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */
185 flcn64_set_dma(&bl_dmem_desc->data_dma_base,
186 acr->acr_ucode.gpu_va +
187 acr_ucode_header_t210_load[2]);
188 bl_dmem_desc->data_size = acr_ucode_header_t210_load[3];
189 } else {
190 acr->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0;
191 }
192 status = pmu_exec_gen_bl(g, bl_dmem_desc, 1);
193 if (status != 0) {
194 err = status;
195 goto err_free_ucode_map;
196 }
197
198 return 0;
199err_free_ucode_map:
200 nvgpu_dma_unmap_free(vm, &acr->acr_ucode);
201err_release_acr_fw:
202 nvgpu_release_firmware(g, acr_fw);
203 acr->acr_fw = NULL;
204
205 return err;
206}
207
208static int bl_bootstrap(struct nvgpu_pmu *pmu,
209 struct flcn_bl_dmem_desc_v1 *pbl_desc, u32 bl_sz)
210{
211 struct gk20a *g = gk20a_from_pmu(pmu);
212 struct mm_gk20a *mm = &g->mm;
213 struct nvgpu_falcon_bl_info bl_info;
214
215 nvgpu_log_fn(g, " ");
216
217 gk20a_writel(g, pwr_falcon_itfen_r(),
218 gk20a_readl(g, pwr_falcon_itfen_r()) |
219 pwr_falcon_itfen_ctxen_enable_f());
220 gk20a_writel(g, pwr_pmu_new_instblk_r(),
221 pwr_pmu_new_instblk_ptr_f(
222 nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
223 pwr_pmu_new_instblk_valid_f(1) |
224 (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ?
225 pwr_pmu_new_instblk_target_sys_coh_f() :
226 pwr_pmu_new_instblk_target_sys_ncoh_f())) ;
227
228 bl_info.bl_src = g->acr.hsbl_ucode.cpu_va;
229 bl_info.bl_desc = (u8 *)pbl_desc;
230 bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
231 bl_info.bl_size = bl_sz;
232 bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag;
233 nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, &bl_info);
234
235 return 0;
236}
237
238void gv11b_setup_apertures(struct gk20a *g) 66void gv11b_setup_apertures(struct gk20a *g)
239{ 67{
240 struct mm_gk20a *mm = &g->mm; 68 struct mm_gk20a *mm = &g->mm;
@@ -263,37 +91,3 @@ void gv11b_setup_apertures(struct gk20a *g)
263 pwr_fbif_transcfg_mem_type_physical_f() | 91 pwr_fbif_transcfg_mem_type_physical_f() |
264 pwr_fbif_transcfg_target_noncoherent_sysmem_f()); 92 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
265} 93}
266
267int gv11b_init_pmu_setup_hw1(struct gk20a *g,
268 void *desc, u32 bl_sz)
269{
270 struct nvgpu_pmu *pmu = &g->pmu;
271 int err;
272
273 nvgpu_log_fn(g, " ");
274
275 nvgpu_mutex_acquire(&pmu->isr_mutex);
276 nvgpu_flcn_reset(pmu->flcn);
277 pmu->isr_enabled = true;
278 nvgpu_mutex_release(&pmu->isr_mutex);
279
280 if (g->ops.pmu.setup_apertures) {
281 g->ops.pmu.setup_apertures(g);
282 }
283 if (g->ops.pmu.update_lspmu_cmdline_args) {
284 g->ops.pmu.update_lspmu_cmdline_args(g);
285 }
286
287 /*disable irqs for hs falcon booting as we will poll for halt*/
288 nvgpu_mutex_acquire(&pmu->isr_mutex);
289 g->ops.pmu.pmu_enable_irq(pmu, false);
290 pmu->isr_enabled = false;
291 nvgpu_mutex_release(&pmu->isr_mutex);
292 /*Clearing mailbox register used to reflect capabilities*/
293 gk20a_writel(g, pwr_falcon_mailbox1_r(), 0);
294 err = bl_bootstrap(pmu, desc, bl_sz);
295 if (err) {
296 return err;
297 }
298 return 0;
299}
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 9444002b..0d9f65bf 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -877,17 +877,10 @@ int gv11b_init_hal(struct gk20a *g)
877 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { 877 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
878 /* Add in ops from gm20b acr */ 878 /* Add in ops from gm20b acr */
879 gops->pmu.prepare_ucode = gp106_prepare_ucode_blob, 879 gops->pmu.prepare_ucode = gp106_prepare_ucode_blob,
880 gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn,
881 gops->pmu.get_wpr = gm20b_wpr_info,
882 gops->pmu.alloc_blob_space = gv11b_alloc_blob_space,
883 gops->pmu.pmu_populate_loader_cfg = 880 gops->pmu.pmu_populate_loader_cfg =
884 gp106_pmu_populate_loader_cfg, 881 gp106_pmu_populate_loader_cfg,
885 gops->pmu.flcn_populate_bl_dmem_desc = 882 gops->pmu.flcn_populate_bl_dmem_desc =
886 gp106_flcn_populate_bl_dmem_desc, 883 gp106_flcn_populate_bl_dmem_desc,
887 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
888 gops->pmu.falcon_clear_halt_interrupt_status =
889 clear_halt_interrupt_status,
890 gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1,
891 gops->pmu.update_lspmu_cmdline_args = 884 gops->pmu.update_lspmu_cmdline_args =
892 gm20b_update_lspmu_cmdline_args; 885 gm20b_update_lspmu_cmdline_args;
893 gops->pmu.setup_apertures = gv11b_setup_apertures; 886 gops->pmu.setup_apertures = gv11b_setup_apertures;
@@ -901,11 +894,9 @@ int gv11b_init_hal(struct gk20a *g)
901 } else { 894 } else {
902 /* Inherit from gk20a */ 895 /* Inherit from gk20a */
903 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, 896 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
904 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
905 897
906 gops->pmu.load_lsfalcon_ucode = NULL; 898 gops->pmu.load_lsfalcon_ucode = NULL;
907 gops->pmu.init_wpr_region = NULL; 899 gops->pmu.init_wpr_region = NULL;
908 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
909 900
910 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; 901 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
911 } 902 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 39ab455b..6f57fddc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1052,12 +1052,6 @@ struct gpu_ops {
1052 void (*dump_secure_fuses)(struct gk20a *g); 1052 void (*dump_secure_fuses)(struct gk20a *g);
1053 int (*reset_engine)(struct gk20a *g, bool do_reset); 1053 int (*reset_engine)(struct gk20a *g, bool do_reset);
1054 bool (*is_engine_in_reset)(struct gk20a *g); 1054 bool (*is_engine_in_reset)(struct gk20a *g);
1055 int (*falcon_wait_for_halt)(struct gk20a *g,
1056 unsigned int timeout);
1057 int (*falcon_clear_halt_interrupt_status)(struct gk20a *g,
1058 unsigned int timeout);
1059 int (*init_falcon_setup_hw)(struct gk20a *g,
1060 void *desc, u32 bl_sz);
1061 bool (*is_lazy_bootstrap)(u32 falcon_id); 1055 bool (*is_lazy_bootstrap)(u32 falcon_id);
1062 bool (*is_priv_load)(u32 falcon_id); 1056 bool (*is_priv_load)(u32 falcon_id);
1063 void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); 1057 void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf);
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 2ec08ae6..56a6b01a 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -604,19 +604,12 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
604 /* Add in ops from gm20b acr */ 604 /* Add in ops from gm20b acr */
605 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported, 605 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported,
606 gops->pmu.prepare_ucode = prepare_ucode_blob, 606 gops->pmu.prepare_ucode = prepare_ucode_blob,
607 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
608 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, 607 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
609 gops->pmu.is_priv_load = gm20b_is_priv_load, 608 gops->pmu.is_priv_load = gm20b_is_priv_load,
610 gops->pmu.get_wpr = gm20b_wpr_info,
611 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
612 gops->pmu.pmu_populate_loader_cfg = 609 gops->pmu.pmu_populate_loader_cfg =
613 gm20b_pmu_populate_loader_cfg, 610 gm20b_pmu_populate_loader_cfg,
614 gops->pmu.flcn_populate_bl_dmem_desc = 611 gops->pmu.flcn_populate_bl_dmem_desc =
615 gm20b_flcn_populate_bl_dmem_desc, 612 gm20b_flcn_populate_bl_dmem_desc,
616 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
617 gops->pmu.falcon_clear_halt_interrupt_status =
618 clear_halt_interrupt_status,
619 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
620 613
621 gops->pmu.init_wpr_region = gm20b_pmu_init_acr; 614 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
622 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; 615 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
@@ -628,12 +621,10 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
628 /* Inherit from gk20a */ 621 /* Inherit from gk20a */
629 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, 622 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
630 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, 623 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
631 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
632 gops->pmu.pmu_nsbootstrap = pmu_bootstrap, 624 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
633 625
634 gops->pmu.load_lsfalcon_ucode = NULL; 626 gops->pmu.load_lsfalcon_ucode = NULL;
635 gops->pmu.init_wpr_region = NULL; 627 gops->pmu.init_wpr_region = NULL;
636 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
637 628
638 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; 629 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
639 } 630 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 16:46:51 -0400