diff options
author | Alex Frid <afrid@nvidia.com> | 2014-08-13 23:37:06 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:57 -0400 |
commit | 7252af5389f8df8c77dd68dba0e3e73f04c433e5 (patch) | |
tree | 139741b8caef42725121b42ff70a9add11f57f7a | |
parent | 08dc7c3584e696f06f10ce496febed0bf4afef05 (diff) |
gpu: nvgpu: Disable GM20b GPCPLL SYNC mode
Disabled GPCPLL SYNC mode after GM20b is switched to bypass clock when
powering down GPU.
Bug 1450787
Change-Id: Ifaec2c562e51c0ae1328b7505faafd19607a77f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/456504
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 78f36692..e4e51220 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -493,6 +493,12 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide) | |||
493 | trim_sys_sel_vco_gpc2clk_out_bypass_f()); | 493 | trim_sys_sel_vco_gpc2clk_out_bypass_f()); |
494 | gk20a_writel(g, trim_sys_sel_vco_r(), cfg); | 494 | gk20a_writel(g, trim_sys_sel_vco_r(), cfg); |
495 | 495 | ||
496 | /* clear SYNC_MODE before disabling PLL */ | ||
497 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | ||
498 | cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(), | ||
499 | trim_sys_gpcpll_cfg_sync_mode_disable_f()); | ||
500 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); | ||
501 | |||
496 | /* disable PLL */ | 502 | /* disable PLL */ |
497 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 503 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
498 | cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(), | 504 | cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(), |