diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-05-30 03:23:58 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-30 20:35:18 -0400 |
commit | 6ff0d4e6ebdf72645b2e8c2631da72b6955200c8 (patch) | |
tree | a5664e9d3ee91fa7d1903647c762c8d28e9dcdd3 | |
parent | e4dc4adb3ba4df03945d8012e43889781a7df972 (diff) |
gpu: nvgpu: disable/preempt TSG for hwpm update
To update hwpm, we currently disable/preempt only one
channel without considering if channel could be part
of a TSG
Hence, use proper APIs to disable/preempt/enable which
will internally handle channel/TSG case
Bug 200203191
Change-Id: I329a3c02d635265775f2081abba8e047f491fe7d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1155838
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0ff20dad..2d88ac53 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1677,12 +1677,16 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1677 | return 0; | 1677 | return 0; |
1678 | } | 1678 | } |
1679 | 1679 | ||
1680 | c->g->ops.fifo.disable_channel(c); | 1680 | ret = gk20a_disable_channel_tsg(g, c); |
1681 | ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid); | ||
1682 | if (ret) { | 1681 | if (ret) { |
1683 | c->g->ops.fifo.enable_channel(c); | 1682 | gk20a_err(dev_from_gk20a(g), "failed to disable channel/TSG\n"); |
1684 | gk20a_err(dev_from_gk20a(g), | 1683 | return ret; |
1685 | "failed to preempt channel\n"); | 1684 | } |
1685 | |||
1686 | ret = gk20a_fifo_preempt(g, c); | ||
1687 | if (ret) { | ||
1688 | gk20a_enable_channel_tsg(g, c); | ||
1689 | gk20a_err(dev_from_gk20a(g), "failed to preempt channel/TSG\n"); | ||
1686 | return ret; | 1690 | return ret; |
1687 | } | 1691 | } |
1688 | 1692 | ||
@@ -1757,7 +1761,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1757 | gk20a_mem_end(g, gr_mem); | 1761 | gk20a_mem_end(g, gr_mem); |
1758 | 1762 | ||
1759 | /* enable channel */ | 1763 | /* enable channel */ |
1760 | c->g->ops.fifo.enable_channel(c); | 1764 | gk20a_enable_channel_tsg(g, c); |
1761 | 1765 | ||
1762 | return 0; | 1766 | return 0; |
1763 | cleanup_pm_buf: | 1767 | cleanup_pm_buf: |
@@ -1766,7 +1770,7 @@ cleanup_pm_buf: | |||
1766 | gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, &pm_ctx->mem); | 1770 | gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, &pm_ctx->mem); |
1767 | memset(&pm_ctx->mem, 0, sizeof(struct mem_desc)); | 1771 | memset(&pm_ctx->mem, 0, sizeof(struct mem_desc)); |
1768 | 1772 | ||
1769 | c->g->ops.fifo.enable_channel(c); | 1773 | gk20a_enable_channel_tsg(g, c); |
1770 | return ret; | 1774 | return ret; |
1771 | } | 1775 | } |
1772 | 1776 | ||