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authorSeema Khowala <seemaj@nvidia.com>2017-05-03 16:36:42 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-05-30 11:43:35 -0400
commit68300d9c027acd4263d56ede497c3dce50625e61 (patch)
treea5990d16148849665849ba7684a7fbbaf85e88b1
parent351793947ba6db2cc382962818680e9858959b86 (diff)
gpu: nvgpu: add enable_exceptions gr ops
This is needed to enable chip specific gr exceptions JIRA GPUT19X-75 Change-Id: I5ca8d0e51d00947c3ab1675bb6331207def433a4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1474851 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c20
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c1
4 files changed, 16 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f246b857..1dff07fa 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -314,6 +314,7 @@ struct gpu_ops {
314 int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc, 314 int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc,
315 u32 gpc_exception); 315 u32 gpc_exception);
316 void (*enable_gpc_exceptions)(struct gk20a *g); 316 void (*enable_gpc_exceptions)(struct gk20a *g);
317 void (*enable_exceptions)(struct gk20a *g);
317 void (*create_gr_sysfs)(struct device *dev); 318 void (*create_gr_sysfs)(struct device *dev);
318 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); 319 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
319 int (*record_sm_error_state)(struct gk20a *g, 320 int (*record_sm_error_state)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index f9c76ae5..2b5d809f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4670,6 +4670,16 @@ static int gr_gk20a_zcull_init_hw(struct gk20a *g, struct gr_gk20a *gr)
4670 return 0; 4670 return 0;
4671} 4671}
4672 4672
4673void gk20a_gr_enable_exceptions(struct gk20a *g)
4674{
4675 gk20a_writel(g, gr_exception_r(), 0xFFFFFFFF);
4676 gk20a_writel(g, gr_exception_en_r(), 0xFFFFFFFF);
4677 gk20a_writel(g, gr_exception1_r(), 0xFFFFFFFF);
4678 gk20a_writel(g, gr_exception1_en_r(), 0xFFFFFFFF);
4679 gk20a_writel(g, gr_exception2_r(), 0xFFFFFFFF);
4680 gk20a_writel(g, gr_exception2_en_r(), 0xFFFFFFFF);
4681}
4682
4673void gk20a_gr_enable_gpc_exceptions(struct gk20a *g) 4683void gk20a_gr_enable_gpc_exceptions(struct gk20a *g)
4674{ 4684{
4675 struct gr_gk20a *gr = &g->gr; 4685 struct gr_gk20a *gr = &g->gr;
@@ -4813,13 +4823,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4813 /* TBD: ECC for L1/SM */ 4823 /* TBD: ECC for L1/SM */
4814 /* TBD: enable per BE exceptions */ 4824 /* TBD: enable per BE exceptions */
4815 4825
4816 /* reset and enable all exceptions */ 4826 /* reset and enable exceptions */
4817 gk20a_writel(g, gr_exception_r(), 0xFFFFFFFF); 4827 g->ops.gr.enable_exceptions(g);
4818 gk20a_writel(g, gr_exception_en_r(), 0xFFFFFFFF);
4819 gk20a_writel(g, gr_exception1_r(), 0xFFFFFFFF);
4820 gk20a_writel(g, gr_exception1_en_r(), 0xFFFFFFFF);
4821 gk20a_writel(g, gr_exception2_r(), 0xFFFFFFFF);
4822 gk20a_writel(g, gr_exception2_en_r(), 0xFFFFFFFF);
4823 4828
4824 gr_gk20a_load_zbc_table(g, gr); 4829 gr_gk20a_load_zbc_table(g, gr);
4825 4830
@@ -9557,6 +9562,7 @@ void gk20a_init_gr_ops(struct gpu_ops *gops)
9557 gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; 9562 gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception;
9558 gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; 9563 gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception;
9559 gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions; 9564 gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions;
9565 gops->gr.enable_exceptions = gk20a_gr_enable_exceptions;
9560 gops->gr.get_lrf_tex_ltc_dram_override = NULL; 9566 gops->gr.get_lrf_tex_ltc_dram_override = NULL;
9561 gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; 9567 gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode;
9562 gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; 9568 gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index c1fba235..79aeb42f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -710,6 +710,7 @@ int gr_gk20a_resume_contexts(struct gk20a *g,
710 struct dbg_session_gk20a *dbg_s, 710 struct dbg_session_gk20a *dbg_s,
711 int *ctx_resident_ch_fd); 711 int *ctx_resident_ch_fd);
712void gk20a_gr_enable_gpc_exceptions(struct gk20a *g); 712void gk20a_gr_enable_gpc_exceptions(struct gk20a *g);
713void gk20a_gr_enable_exceptions(struct gk20a *g);
713int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch); 714int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch);
714int gr_gk20a_trigger_suspend(struct gk20a *g); 715int gr_gk20a_trigger_suspend(struct gk20a *g);
715int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state); 716int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state);
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 99bccd0e..e7b6fa85 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1595,6 +1595,7 @@ void gm20b_init_gr(struct gpu_ops *gops)
1595 gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; 1595 gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception;
1596 gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; 1596 gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception;
1597 gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions; 1597 gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions;
1598 gops->gr.enable_exceptions = gk20a_gr_enable_exceptions;
1598 gops->gr.get_lrf_tex_ltc_dram_override = NULL; 1599 gops->gr.get_lrf_tex_ltc_dram_override = NULL;
1599 gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; 1600 gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode;
1600 gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; 1601 gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode;