diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 20:04:05 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:07:00 -0400 |
commit | 5e17dc9419c05188646aeaec93fa83b3f80ac60d (patch) | |
tree | 89fa74c98efaa6396fc340a4c9284d1a2e07b102 | |
parent | 1ab0eec6eae303fa2b2f7cc97b78aed4a9f895e5 (diff) |
gpu: nvgpu: add resume_all_sms gr ops
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: I844b5cf02a75ba397891a1100d917875e5a3e181
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512217
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 |
5 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index aae54cc2..7dd4a9fa 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -377,6 +377,7 @@ struct gpu_ops { | |||
377 | u32 global_esr_mask, bool check_errors); | 377 | u32 global_esr_mask, bool check_errors); |
378 | void (*resume_single_sm)(struct gk20a *g, | 378 | void (*resume_single_sm)(struct gk20a *g, |
379 | u32 gpc, u32 tpc, u32 sm); | 379 | u32 gpc, u32 tpc, u32 sm); |
380 | void (*resume_all_sms)(struct gk20a *g); | ||
380 | } gr; | 381 | } gr; |
381 | struct { | 382 | struct { |
382 | void (*init_hw)(struct gk20a *g); | 383 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 70abef78..42a807f6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8123,7 +8123,7 @@ void gk20a_gr_resume_single_sm(struct gk20a *g, | |||
8123 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); | 8123 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); |
8124 | } | 8124 | } |
8125 | 8125 | ||
8126 | void gk20a_resume_all_sms(struct gk20a *g) | 8126 | void gk20a_gr_resume_all_sms(struct gk20a *g) |
8127 | { | 8127 | { |
8128 | u32 dbgr_control0; | 8128 | u32 dbgr_control0; |
8129 | /* | 8129 | /* |
@@ -8236,7 +8236,7 @@ bool gr_gk20a_resume_context(struct channel_gk20a *ch) | |||
8236 | bool ctx_resident = false; | 8236 | bool ctx_resident = false; |
8237 | 8237 | ||
8238 | if (gk20a_is_channel_ctx_resident(ch)) { | 8238 | if (gk20a_is_channel_ctx_resident(ch)) { |
8239 | gk20a_resume_all_sms(g); | 8239 | g->ops.gr.resume_all_sms(g); |
8240 | ctx_resident = true; | 8240 | ctx_resident = true; |
8241 | } else { | 8241 | } else { |
8242 | gk20a_enable_channel_tsg(g, ch); | 8242 | gk20a_enable_channel_tsg(g, ch); |
@@ -8438,7 +8438,7 @@ int gr_gk20a_resume_from_pause(struct gk20a *g) | |||
8438 | 8438 | ||
8439 | /* Now resume all sms, write a 0 to the stop trigger | 8439 | /* Now resume all sms, write a 0 to the stop trigger |
8440 | * then a 1 to the run trigger */ | 8440 | * then a 1 to the run trigger */ |
8441 | gk20a_resume_all_sms(g); | 8441 | g->ops.gr.resume_all_sms(g); |
8442 | 8442 | ||
8443 | return err; | 8443 | return err; |
8444 | } | 8444 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 659b37a6..5a28deea 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -614,7 +614,7 @@ int gr_gk20a_disable_ctxsw(struct gk20a *g); | |||
614 | int gr_gk20a_enable_ctxsw(struct gk20a *g); | 614 | int gr_gk20a_enable_ctxsw(struct gk20a *g); |
615 | void gk20a_gr_resume_single_sm(struct gk20a *g, | 615 | void gk20a_gr_resume_single_sm(struct gk20a *g, |
616 | u32 gpc, u32 tpc, u32 sm); | 616 | u32 gpc, u32 tpc, u32 sm); |
617 | void gk20a_resume_all_sms(struct gk20a *g); | 617 | void gk20a_gr_resume_all_sms(struct gk20a *g); |
618 | void gk20a_gr_suspend_single_sm(struct gk20a *g, | 618 | void gk20a_gr_suspend_single_sm(struct gk20a *g, |
619 | u32 gpc, u32 tpc, u32 sm, | 619 | u32 gpc, u32 tpc, u32 sm, |
620 | u32 global_esr_mask, bool check_errors); | 620 | u32 global_esr_mask, bool check_errors); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 04c8824b..5fac9ac8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1634,4 +1634,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1634 | gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm; | 1634 | gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm; |
1635 | gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms; | 1635 | gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms; |
1636 | gops->gr.resume_single_sm = gk20a_gr_resume_single_sm; | 1636 | gops->gr.resume_single_sm = gk20a_gr_resume_single_sm; |
1637 | gops->gr.resume_all_sms = gk20a_gr_resume_all_sms; | ||
1637 | } | 1638 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a1be22df..e3ea4603 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -2000,7 +2000,7 @@ static bool gr_gp10b_suspend_context(struct channel_gk20a *ch, | |||
2000 | else | 2000 | else |
2001 | *cilp_preempt_pending = true; | 2001 | *cilp_preempt_pending = true; |
2002 | 2002 | ||
2003 | gk20a_resume_all_sms(g); | 2003 | g->ops.gr.resume_all_sms(g); |
2004 | } | 2004 | } |
2005 | 2005 | ||
2006 | ctx_resident = true; | 2006 | ctx_resident = true; |