gpu: nvgpu: Determine ECC-enabled units for GP10B

Determine ECC-enabled units for GP10B by reading fuses/registers.

Bug 1637486

Change-Id: I6431709e3c405d6156dd96438df14d4054b48644
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/780992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120463
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

7 files changed, 198 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index e5ed32d4..13d52f84 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -17,7 +17,8 @@ nvgpu-y += \
         $(nvgpu-t18x)/gp10b/cde_gp10b.o \
         $(nvgpu-t18x)/gp10b/therm_gp10b.o \
         $(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \
-        $(nvgpu-t18x)/gp10b/gp10b_sysfs.o
+        $(nvgpu-t18x)/gp10b/gp10b_sysfs.o \
+        $(nvgpu-t18x)/gp10b/gp10b.o
 
 nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o
 
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c
new file mode 100644
index 00000000..a541dda3
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b.c
@@ -0,0 +1,110 @@
+/*
+ * GP10B Graphics
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "gk20a/gk20a.h"
+#include "hw_fuse_gp10b.h"
+#include "hw_gr_gp10b.h"
+
+static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
+{
+        u64 ecc_enabled_units = 0;
+        u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
+        u32 opt_feature_fuses_override_disable =
+                        gk20a_readl(g,
+                                fuse_opt_feature_fuses_override_disable_r());
+        u32 fecs_feature_override_ecc =
+                                gk20a_readl(g,
+                                        gr_fecs_feature_override_ecc_r());
+
+        if (opt_feature_fuses_override_disable) {
+                if (opt_ecc_en)
+                        ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED;
+                else
+                        ecc_enabled_units = 0;
+        } else {
+                /* SM LRF */
+                if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
+                                                fecs_feature_override_ecc)) {
+                        if (gr_fecs_feature_override_ecc_sm_lrf_v(
+                                                fecs_feature_override_ecc)) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
+                        }
+                } else {
+                        if (opt_ecc_en) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
+                        }
+                }
+
+                /* SM SHM */
+                if (gr_fecs_feature_override_ecc_sm_shm_override_v(
+                                                fecs_feature_override_ecc)) {
+                        if (gr_fecs_feature_override_ecc_sm_shm_v(
+                                                fecs_feature_override_ecc)) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
+                        }
+                } else {
+                        if (opt_ecc_en) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
+                        }
+                }
+
+                /* TEX */
+                if (gr_fecs_feature_override_ecc_tex_override_v(
+                                                fecs_feature_override_ecc)) {
+                        if (gr_fecs_feature_override_ecc_tex_v(
+                                                fecs_feature_override_ecc)) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
+                        }
+                } else {
+                        if (opt_ecc_en) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
+                        }
+                }
+
+                /* LTC */
+                if (gr_fecs_feature_override_ecc_ltc_override_v(
+                                                fecs_feature_override_ecc)) {
+                        if (gr_fecs_feature_override_ecc_ltc_v(
+                                                fecs_feature_override_ecc)) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
+                        }
+                } else {
+                        if (opt_ecc_en) {
+                                ecc_enabled_units |=
+                                        NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
+                        }
+                }
+        }
+
+        return ecc_enabled_units;
+}
+
+int gp10b_init_gpu_characteristics(struct gk20a *g)
+{
+        gk20a_init_gpu_characteristics(g);
+        g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g);
+
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.h b/drivers/gpu/nvgpu/gp10b/gp10b.h
new file mode 100644
index 00000000..263f3cbe
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b.h
@@ -0,0 +1,26 @@
+/*
+ * GP10B Graphics
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef GP10B_H
+#define GP10B_H
+
+#include "gk20a/gk20a.h"
+
+int gp10b_init_gpu_characteristics(struct gk20a *g);
+
+#endif /* GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 4f67cb09..427936c7 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -41,6 +41,8 @@
 #include "gm20b/clk_gm20b.h"
 #include <linux/tegra-fuse.h>
 
+#include "gp10b.h"
+
 #define FUSE_OPT_PRIV_SEC_EN_0 0x264
 #define PRIV_SECURITY_ENABLED 0x01
 
@@ -153,6 +155,7 @@ int gp10b_init_hal(struct gk20a *g)
         gp10b_init_cde_ops(gops);
         gp10b_init_therm_ops(gops);
         gops->name = "gp10b";
+        gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
 
         c->twod_class = FERMI_TWOD_A;
         c->threed_class = PASCAL_A;
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h
index b6b68718..ae524ce5 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -126,4 +126,12 @@ static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
 {
         return (r >> (0 + i*0)) & 0x1;
 }
+static inline u32 fuse_opt_ecc_en_r(void)
+{
+        return 0x00021228;
+}
+static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
+{
+        return 0x000213f0;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 26578bb5..b3fd704b 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1486,6 +1486,38 @@ static inline u32 gr_fecs_feature_override_ecc_r(void)
 {
         return 0x00409658;
 }
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
+{
+        return (r >> 3) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r)
+{
+        return (r >> 7) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r)
+{
+        return (r >> 11) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
+{
+        return (r >> 15) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
+{
+        return (r >> 0) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r)
+{
+        return (r >> 4) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r)
+{
+        return (r >> 8) & 0x1;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
+{
+        return (r >> 12) & 0x1;
+}
 static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
 {
         return 0x00502420;
diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h
index b2a75143..6116ec61 100644
--- a/include/uapi/linux/nvgpu-t18x.h
+++ b/include/uapi/linux/nvgpu-t18x.h
@@ -1,7 +1,7 @@
 /*
  * NVGPU Public Interface Header
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -43,6 +43,21 @@
 #define NVGPU_ALLOC_OBJ_FLAGS_GFXP              (1 << 1)
 #define NVGPU_ALLOC_OBJ_FLAGS_CILP              (1 << 2)
 
+/* SM LRF ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF      (1ULL << 60)
+/* SM SHM ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM      (1ULL << 61)
+/* TEX ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX         (1ULL << 62)
+/* L2 ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC         (1ULL << 63)
+/* All types of ECC are enabled */
+#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \
+                                (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF |   \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_TEX    |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_LTC)
+
 #endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */