diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2014-12-08 07:07:39 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:27 -0400 |
commit | 5477d0f4c226847fe030ad00425e00206118b0d6 (patch) | |
tree | f9009dd92f5e4096a75ca126f177c52f77778fde | |
parent | 69bb5e156944d5df715d6bb388fd1c97fe458f18 (diff) |
gpu: nvgpu: Generic mem_desc & allocation
Make mem_desc a generic container for buffers. Add functions for
allocating and mapping buffers to an address space which store their
data in mem_desc.
Change-Id: I031643442c6fd41f5e7222fe9b7bfcaf9b784db5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660908
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 22 |
4 files changed, 62 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 263ca291..c60afb97 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -59,7 +59,6 @@ struct fence { | |||
59 | /* contexts associated with a channel */ | 59 | /* contexts associated with a channel */ |
60 | struct channel_ctx_gk20a { | 60 | struct channel_ctx_gk20a { |
61 | struct gr_ctx_desc *gr_ctx; | 61 | struct gr_ctx_desc *gr_ctx; |
62 | struct pm_ctx_desc pm_ctx; | ||
63 | struct patch_desc patch_ctx; | 62 | struct patch_desc patch_ctx; |
64 | struct zcull_ctx_desc zcull_ctx; | 63 | struct zcull_ctx_desc zcull_ctx; |
65 | u64 global_ctx_buffer_va[NR_GLOBAL_CTX_BUF_VA]; | 64 | u64 global_ctx_buffer_va[NR_GLOBAL_CTX_BUF_VA]; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f2b0c83c..867e775a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1618,11 +1618,9 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1618 | virt_addr_hi); | 1618 | virt_addr_hi); |
1619 | 1619 | ||
1620 | /* no user for client managed performance counter ctx */ | 1620 | /* no user for client managed performance counter ctx */ |
1621 | ch_ctx->pm_ctx.ctx_sw_mode = | ||
1622 | ctxsw_prog_main_image_pm_mode_no_ctxsw_f(); | ||
1623 | data = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_pm_o(), 0); | 1621 | data = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_pm_o(), 0); |
1624 | data = data & ~ctxsw_prog_main_image_pm_mode_m(); | 1622 | data = data & ~ctxsw_prog_main_image_pm_mode_m(); |
1625 | data |= ch_ctx->pm_ctx.ctx_sw_mode; | 1623 | data |= ctxsw_prog_main_image_pm_mode_no_ctxsw_f(); |
1626 | gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_pm_o(), 0, | 1624 | gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_pm_o(), 0, |
1627 | data); | 1625 | data); |
1628 | 1626 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 9fdbf2b7..5e925d65 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -1546,6 +1546,56 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm, | |||
1546 | return vaddr; | 1546 | return vaddr; |
1547 | } | 1547 | } |
1548 | 1548 | ||
1549 | int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, | ||
1550 | size_t size, struct mem_desc *mem) | ||
1551 | { | ||
1552 | struct gk20a *g = vm->mm->g; | ||
1553 | struct device *d = dev_from_gk20a(g); | ||
1554 | int err; | ||
1555 | struct sg_table *sgt; | ||
1556 | |||
1557 | mem->cpu_va = dma_alloc_coherent(d, size, &mem->iova, GFP_KERNEL); | ||
1558 | if (!mem->cpu_va) | ||
1559 | return -ENOMEM; | ||
1560 | |||
1561 | err = gk20a_get_sgtable(d, &sgt, mem->cpu_va, mem->iova, size); | ||
1562 | if (err) | ||
1563 | goto fail_free; | ||
1564 | |||
1565 | mem->gpu_va = gk20a_gmmu_map(vm, &sgt, size, 0, gk20a_mem_flag_none); | ||
1566 | gk20a_free_sgtable(&sgt); | ||
1567 | if (!mem->gpu_va) { | ||
1568 | err = -ENOMEM; | ||
1569 | goto fail_free; | ||
1570 | } | ||
1571 | |||
1572 | mem->size = size; | ||
1573 | |||
1574 | return 0; | ||
1575 | |||
1576 | fail_free: | ||
1577 | dma_free_coherent(d, size, mem->cpu_va, mem->iova); | ||
1578 | mem->cpu_va = NULL; | ||
1579 | mem->iova = 0; | ||
1580 | |||
1581 | return err; | ||
1582 | } | ||
1583 | |||
1584 | void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, struct mem_desc *mem) | ||
1585 | { | ||
1586 | struct gk20a *g = vm->mm->g; | ||
1587 | struct device *d = dev_from_gk20a(g); | ||
1588 | |||
1589 | if (mem->gpu_va) | ||
1590 | gk20a_gmmu_unmap(vm, mem->gpu_va, mem->size, gk20a_mem_flag_none); | ||
1591 | mem->gpu_va = 0; | ||
1592 | |||
1593 | if (mem->cpu_va) | ||
1594 | dma_free_coherent(d, mem->size, mem->cpu_va, mem->iova); | ||
1595 | mem->cpu_va = NULL; | ||
1596 | mem->iova = 0; | ||
1597 | } | ||
1598 | |||
1549 | dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr) | 1599 | dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr) |
1550 | { | 1600 | { |
1551 | struct mapped_buffer_node *buffer; | 1601 | struct mapped_buffer_node *buffer; |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index d6cb74de..041c7edf 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -42,9 +42,10 @@ | |||
42 | } while (0) | 42 | } while (0) |
43 | 43 | ||
44 | struct mem_desc { | 44 | struct mem_desc { |
45 | struct dma_buf *ref; | 45 | void *cpu_va; |
46 | struct sg_table *sgt; | 46 | dma_addr_t iova; |
47 | u32 size; | 47 | size_t size; |
48 | u64 gpu_va; | ||
48 | }; | 49 | }; |
49 | 50 | ||
50 | struct mem_desc_sub { | 51 | struct mem_desc_sub { |
@@ -123,14 +124,6 @@ struct priv_cmd_queue_mem_desc { | |||
123 | }; | 124 | }; |
124 | 125 | ||
125 | struct zcull_ctx_desc { | 126 | struct zcull_ctx_desc { |
126 | struct mem_desc mem; | ||
127 | u64 gpu_va; | ||
128 | u32 ctx_attr; | ||
129 | u32 ctx_sw_mode; | ||
130 | }; | ||
131 | |||
132 | struct pm_ctx_desc { | ||
133 | struct mem_desc mem; | ||
134 | u64 gpu_va; | 127 | u64 gpu_va; |
135 | u32 ctx_attr; | 128 | u32 ctx_attr; |
136 | u32 ctx_sw_mode; | 129 | u32 ctx_sw_mode; |
@@ -427,6 +420,13 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm, | |||
427 | u32 flags, | 420 | u32 flags, |
428 | int rw_flag); | 421 | int rw_flag); |
429 | 422 | ||
423 | int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, | ||
424 | size_t size, | ||
425 | struct mem_desc *mem); | ||
426 | |||
427 | void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, | ||
428 | struct mem_desc *mem); | ||
429 | |||
430 | u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, | 430 | u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, |
431 | u64 map_offset, | 431 | u64 map_offset, |
432 | struct sg_table *sgt, | 432 | struct sg_table *sgt, |