diff options
author | Debarshi Dutta <ddutta@nvidia.com> | 2017-11-13 03:21:48 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-23 06:03:36 -0500 |
commit | 536ec21b565ab1368b53a26d6ec7ed05857f0775 (patch) | |
tree | 5f385385ae730dd2d98463502d249150262f8b9b | |
parent | ba2e59dc41f593bb011e0ec58c969337a35f4cf1 (diff) |
gpu: nvgpu: remove dependency on linux header for regops_gk20a*
This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.
1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.
JIRA NVGPU-417
Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/driver_common.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_dbg.c | 230 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.h | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 |
12 files changed, 297 insertions, 29 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c index 9e567c27..45b53d88 100644 --- a/drivers/gpu/nvgpu/common/linux/driver_common.c +++ b/drivers/gpu/nvgpu/common/linux/driver_common.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "os_linux.h" | 31 | #include "os_linux.h" |
32 | #include "sysfs.h" | 32 | #include "sysfs.h" |
33 | #include "ioctl.h" | 33 | #include "ioctl.h" |
34 | #include "gk20a/regops_gk20a.h" | ||
34 | 35 | ||
35 | #define EMC3D_DEFAULT_RATIO 750 | 36 | #define EMC3D_DEFAULT_RATIO 750 |
36 | 37 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c index 304fd71f..4bade485 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c | |||
@@ -40,6 +40,8 @@ | |||
40 | #include "platform_gk20a.h" | 40 | #include "platform_gk20a.h" |
41 | #include "ioctl_dbg.h" | 41 | #include "ioctl_dbg.h" |
42 | 42 | ||
43 | /* turn seriously unwieldy names -> something shorter */ | ||
44 | #define REGOP_LINUX(x) NVGPU_DBG_GPU_REG_OP_##x | ||
43 | 45 | ||
44 | /* silly allocator - just increment id */ | 46 | /* silly allocator - just increment id */ |
45 | static nvgpu_atomic_t unique_id = NVGPU_ATOMIC_INIT(0); | 47 | static nvgpu_atomic_t unique_id = NVGPU_ATOMIC_INIT(0); |
@@ -596,6 +598,204 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s) | |||
596 | return 0; | 598 | return 0; |
597 | } | 599 | } |
598 | 600 | ||
601 | /* | ||
602 | * Convert common regops op values of the form of NVGPU_DBG_REG_OP_* | ||
603 | * into linux regops op values of the form of NVGPU_DBG_GPU_REG_OP_* | ||
604 | */ | ||
605 | static u32 nvgpu_get_regops_op_values_linux(u32 regops_op) | ||
606 | { | ||
607 | switch (regops_op) { | ||
608 | case REGOP(READ_32): | ||
609 | return REGOP_LINUX(READ_32); | ||
610 | case REGOP(WRITE_32): | ||
611 | return REGOP_LINUX(WRITE_32); | ||
612 | case REGOP(READ_64): | ||
613 | return REGOP_LINUX(READ_64); | ||
614 | case REGOP(WRITE_64): | ||
615 | return REGOP_LINUX(WRITE_64); | ||
616 | case REGOP(READ_08): | ||
617 | return REGOP_LINUX(READ_08); | ||
618 | case REGOP(WRITE_08): | ||
619 | return REGOP_LINUX(WRITE_08); | ||
620 | } | ||
621 | |||
622 | return regops_op; | ||
623 | } | ||
624 | |||
625 | /* | ||
626 | * Convert linux regops op values of the form of NVGPU_DBG_GPU_REG_OP_* | ||
627 | * into common regops op values of the form of NVGPU_DBG_REG_OP_* | ||
628 | */ | ||
629 | static u32 nvgpu_get_regops_op_values_common(u32 regops_op) | ||
630 | { | ||
631 | switch (regops_op) { | ||
632 | case REGOP_LINUX(READ_32): | ||
633 | return REGOP(READ_32); | ||
634 | case REGOP_LINUX(WRITE_32): | ||
635 | return REGOP(WRITE_32); | ||
636 | case REGOP_LINUX(READ_64): | ||
637 | return REGOP(READ_64); | ||
638 | case REGOP_LINUX(WRITE_64): | ||
639 | return REGOP(WRITE_64); | ||
640 | case REGOP_LINUX(READ_08): | ||
641 | return REGOP(READ_08); | ||
642 | case REGOP_LINUX(WRITE_08): | ||
643 | return REGOP(WRITE_08); | ||
644 | } | ||
645 | |||
646 | return regops_op; | ||
647 | } | ||
648 | |||
649 | /* | ||
650 | * Convert common regops type values of the form of NVGPU_DBG_REG_OP_TYPE_* | ||
651 | * into linux regops type values of the form of NVGPU_DBG_GPU_REG_OP_TYPE_* | ||
652 | */ | ||
653 | static u32 nvgpu_get_regops_type_values_linux(u32 regops_type) | ||
654 | { | ||
655 | switch (regops_type) { | ||
656 | case REGOP(TYPE_GLOBAL): | ||
657 | return REGOP_LINUX(TYPE_GLOBAL); | ||
658 | case REGOP(TYPE_GR_CTX): | ||
659 | return REGOP_LINUX(TYPE_GR_CTX); | ||
660 | case REGOP(TYPE_GR_CTX_TPC): | ||
661 | return REGOP_LINUX(TYPE_GR_CTX_TPC); | ||
662 | case REGOP(TYPE_GR_CTX_SM): | ||
663 | return REGOP_LINUX(TYPE_GR_CTX_SM); | ||
664 | case REGOP(TYPE_GR_CTX_CROP): | ||
665 | return REGOP_LINUX(TYPE_GR_CTX_CROP); | ||
666 | case REGOP(TYPE_GR_CTX_ZROP): | ||
667 | return REGOP_LINUX(TYPE_GR_CTX_ZROP); | ||
668 | case REGOP(TYPE_GR_CTX_QUAD): | ||
669 | return REGOP_LINUX(TYPE_GR_CTX_QUAD); | ||
670 | } | ||
671 | |||
672 | return regops_type; | ||
673 | } | ||
674 | |||
675 | /* | ||
676 | * Convert linux regops type values of the form of NVGPU_DBG_GPU_REG_OP_TYPE_* | ||
677 | * into common regops type values of the form of NVGPU_DBG_REG_OP_TYPE_* | ||
678 | */ | ||
679 | static u32 nvgpu_get_regops_type_values_common(u32 regops_type) | ||
680 | { | ||
681 | switch (regops_type) { | ||
682 | case REGOP_LINUX(TYPE_GLOBAL): | ||
683 | return REGOP(TYPE_GLOBAL); | ||
684 | case REGOP_LINUX(TYPE_GR_CTX): | ||
685 | return REGOP(TYPE_GR_CTX); | ||
686 | case REGOP_LINUX(TYPE_GR_CTX_TPC): | ||
687 | return REGOP(TYPE_GR_CTX_TPC); | ||
688 | case REGOP_LINUX(TYPE_GR_CTX_SM): | ||
689 | return REGOP(TYPE_GR_CTX_SM); | ||
690 | case REGOP_LINUX(TYPE_GR_CTX_CROP): | ||
691 | return REGOP(TYPE_GR_CTX_CROP); | ||
692 | case REGOP_LINUX(TYPE_GR_CTX_ZROP): | ||
693 | return REGOP(TYPE_GR_CTX_ZROP); | ||
694 | case REGOP_LINUX(TYPE_GR_CTX_QUAD): | ||
695 | return REGOP(TYPE_GR_CTX_QUAD); | ||
696 | } | ||
697 | |||
698 | return regops_type; | ||
699 | } | ||
700 | |||
701 | /* | ||
702 | * Convert common regops status values of the form of NVGPU_DBG_REG_OP_STATUS_* | ||
703 | * into linux regops type values of the form of NVGPU_DBG_GPU_REG_OP_STATUS_* | ||
704 | */ | ||
705 | static u32 nvgpu_get_regops_status_values_linux(u32 regops_status) | ||
706 | { | ||
707 | switch (regops_status) { | ||
708 | case REGOP(STATUS_SUCCESS): | ||
709 | return REGOP_LINUX(STATUS_SUCCESS); | ||
710 | case REGOP(STATUS_INVALID_OP): | ||
711 | return REGOP_LINUX(STATUS_INVALID_OP); | ||
712 | case REGOP(STATUS_INVALID_TYPE): | ||
713 | return REGOP_LINUX(STATUS_INVALID_TYPE); | ||
714 | case REGOP(STATUS_INVALID_OFFSET): | ||
715 | return REGOP_LINUX(STATUS_INVALID_OFFSET); | ||
716 | case REGOP(STATUS_UNSUPPORTED_OP): | ||
717 | return REGOP_LINUX(STATUS_UNSUPPORTED_OP); | ||
718 | case REGOP(STATUS_INVALID_MASK ): | ||
719 | return REGOP_LINUX(STATUS_INVALID_MASK); | ||
720 | } | ||
721 | |||
722 | return regops_status; | ||
723 | } | ||
724 | |||
725 | /* | ||
726 | * Convert linux regops status values of the form of NVGPU_DBG_GPU_REG_OP_STATUS_* | ||
727 | * into common regops type values of the form of NVGPU_DBG_REG_OP_STATUS_* | ||
728 | */ | ||
729 | static u32 nvgpu_get_regops_status_values_common(u32 regops_status) | ||
730 | { | ||
731 | switch (regops_status) { | ||
732 | case REGOP_LINUX(STATUS_SUCCESS): | ||
733 | return REGOP(STATUS_SUCCESS); | ||
734 | case REGOP_LINUX(STATUS_INVALID_OP): | ||
735 | return REGOP(STATUS_INVALID_OP); | ||
736 | case REGOP_LINUX(STATUS_INVALID_TYPE): | ||
737 | return REGOP(STATUS_INVALID_TYPE); | ||
738 | case REGOP_LINUX(STATUS_INVALID_OFFSET): | ||
739 | return REGOP(STATUS_INVALID_OFFSET); | ||
740 | case REGOP_LINUX(STATUS_UNSUPPORTED_OP): | ||
741 | return REGOP(STATUS_UNSUPPORTED_OP); | ||
742 | case REGOP_LINUX(STATUS_INVALID_MASK ): | ||
743 | return REGOP(STATUS_INVALID_MASK); | ||
744 | } | ||
745 | |||
746 | return regops_status; | ||
747 | } | ||
748 | |||
749 | static int nvgpu_get_regops_data_common(struct nvgpu_dbg_gpu_reg_op *in, | ||
750 | struct nvgpu_dbg_reg_op *out, u32 num_ops) | ||
751 | { | ||
752 | u32 i; | ||
753 | |||
754 | if(in == NULL || out == NULL) | ||
755 | return -ENOMEM; | ||
756 | |||
757 | for (i = 0; i < num_ops; i++) { | ||
758 | out[i].op = nvgpu_get_regops_op_values_common(in[i].op); | ||
759 | out[i].type = nvgpu_get_regops_type_values_common(in[i].type); | ||
760 | out[i].status = nvgpu_get_regops_status_values_common(in[i].status); | ||
761 | out[i].quad = in[i].quad; | ||
762 | out[i].group_mask = in[i].group_mask; | ||
763 | out[i].sub_group_mask = in[i].sub_group_mask; | ||
764 | out[i].offset = in[i].offset; | ||
765 | out[i].value_lo = in[i].value_lo; | ||
766 | out[i].value_hi = in[i].value_hi; | ||
767 | out[i].and_n_mask_lo = in[i].and_n_mask_lo; | ||
768 | out[i].and_n_mask_hi = in[i].and_n_mask_hi; | ||
769 | } | ||
770 | |||
771 | return 0; | ||
772 | } | ||
773 | |||
774 | static int nvgpu_get_regops_data_linux(struct nvgpu_dbg_reg_op *in, | ||
775 | struct nvgpu_dbg_gpu_reg_op *out, u32 num_ops) | ||
776 | { | ||
777 | u32 i; | ||
778 | |||
779 | if(in == NULL || out == NULL) | ||
780 | return -ENOMEM; | ||
781 | |||
782 | for (i = 0; i < num_ops; i++) { | ||
783 | out[i].op = nvgpu_get_regops_op_values_linux(in[i].op); | ||
784 | out[i].type = nvgpu_get_regops_type_values_linux(in[i].type); | ||
785 | out[i].status = nvgpu_get_regops_status_values_linux(in[i].status); | ||
786 | out[i].quad = in[i].quad; | ||
787 | out[i].group_mask = in[i].group_mask; | ||
788 | out[i].sub_group_mask = in[i].sub_group_mask; | ||
789 | out[i].offset = in[i].offset; | ||
790 | out[i].value_lo = in[i].value_lo; | ||
791 | out[i].value_hi = in[i].value_hi; | ||
792 | out[i].and_n_mask_lo = in[i].and_n_mask_lo; | ||
793 | out[i].and_n_mask_hi = in[i].and_n_mask_hi; | ||
794 | } | ||
795 | |||
796 | return 0; | ||
797 | } | ||
798 | |||
599 | static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | 799 | static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, |
600 | struct nvgpu_dbg_gpu_exec_reg_ops_args *args) | 800 | struct nvgpu_dbg_gpu_exec_reg_ops_args *args) |
601 | { | 801 | { |
@@ -657,36 +857,56 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
657 | if (!powergate_err) { | 857 | if (!powergate_err) { |
658 | u64 ops_offset = 0; /* index offset */ | 858 | u64 ops_offset = 0; /* index offset */ |
659 | 859 | ||
860 | struct nvgpu_dbg_gpu_reg_op *linux_fragment = NULL; | ||
861 | |||
862 | linux_fragment = nvgpu_kzalloc(g, g->dbg_regops_tmp_buf_ops * | ||
863 | sizeof(struct nvgpu_dbg_gpu_reg_op)); | ||
864 | |||
865 | if (!linux_fragment) | ||
866 | return -ENOMEM; | ||
867 | |||
660 | while (ops_offset < args->num_ops && !err) { | 868 | while (ops_offset < args->num_ops && !err) { |
661 | const u64 num_ops = | 869 | const u64 num_ops = |
662 | min(args->num_ops - ops_offset, | 870 | min(args->num_ops - ops_offset, |
663 | (u64)(g->dbg_regops_tmp_buf_ops)); | 871 | (u64)(g->dbg_regops_tmp_buf_ops)); |
664 | const u64 fragment_size = | 872 | const u64 fragment_size = |
665 | num_ops * sizeof(g->dbg_regops_tmp_buf[0]); | 873 | num_ops * sizeof(struct nvgpu_dbg_gpu_reg_op); |
666 | 874 | ||
667 | void __user *const fragment = | 875 | void __user *const fragment = |
668 | (void __user *)(uintptr_t) | 876 | (void __user *)(uintptr_t) |
669 | (args->ops + | 877 | (args->ops + |
670 | ops_offset * sizeof(g->dbg_regops_tmp_buf[0])); | 878 | ops_offset * sizeof(struct nvgpu_dbg_gpu_reg_op)); |
671 | 879 | ||
672 | gk20a_dbg_fn("Regops fragment: start_op=%llu ops=%llu", | 880 | gk20a_dbg_fn("Regops fragment: start_op=%llu ops=%llu", |
673 | ops_offset, num_ops); | 881 | ops_offset, num_ops); |
674 | 882 | ||
675 | gk20a_dbg_fn("Copying regops from userspace"); | 883 | gk20a_dbg_fn("Copying regops from userspace"); |
676 | 884 | ||
677 | if (copy_from_user(g->dbg_regops_tmp_buf, | 885 | if (copy_from_user(linux_fragment, |
678 | fragment, fragment_size)) { | 886 | fragment, fragment_size)) { |
679 | nvgpu_err(g, "copy_from_user failed!"); | 887 | nvgpu_err(g, "copy_from_user failed!"); |
680 | err = -EFAULT; | 888 | err = -EFAULT; |
681 | break; | 889 | break; |
682 | } | 890 | } |
683 | 891 | ||
892 | err = nvgpu_get_regops_data_common(linux_fragment, | ||
893 | g->dbg_regops_tmp_buf, num_ops); | ||
894 | |||
895 | if (err) | ||
896 | break; | ||
897 | |||
684 | err = g->ops.dbg_session_ops.exec_reg_ops( | 898 | err = g->ops.dbg_session_ops.exec_reg_ops( |
685 | dbg_s, g->dbg_regops_tmp_buf, num_ops); | 899 | dbg_s, g->dbg_regops_tmp_buf, num_ops); |
686 | 900 | ||
901 | err = nvgpu_get_regops_data_linux(g->dbg_regops_tmp_buf, | ||
902 | linux_fragment, num_ops); | ||
903 | |||
904 | if (err) | ||
905 | break; | ||
906 | |||
687 | gk20a_dbg_fn("Copying result to userspace"); | 907 | gk20a_dbg_fn("Copying result to userspace"); |
688 | 908 | ||
689 | if (copy_to_user(fragment, g->dbg_regops_tmp_buf, | 909 | if (copy_to_user(fragment, linux_fragment, |
690 | fragment_size)) { | 910 | fragment_size)) { |
691 | nvgpu_err(g, "copy_to_user failed!"); | 911 | nvgpu_err(g, "copy_to_user failed!"); |
692 | err = -EFAULT; | 912 | err = -EFAULT; |
@@ -696,6 +916,8 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
696 | ops_offset += num_ops; | 916 | ops_offset += num_ops; |
697 | } | 917 | } |
698 | 918 | ||
919 | nvgpu_kfree(g, linux_fragment); | ||
920 | |||
699 | /* enable powergate, if previously disabled */ | 921 | /* enable powergate, if previously disabled */ |
700 | if (is_pg_disabled) { | 922 | if (is_pg_disabled) { |
701 | powergate_err = | 923 | powergate_err = |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c index 06ef43b8..dfdbe3ee 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c | |||
@@ -21,13 +21,14 @@ | |||
21 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
22 | #include "gk20a/channel_gk20a.h" | 22 | #include "gk20a/channel_gk20a.h" |
23 | #include "gk20a/dbg_gpu_gk20a.h" | 23 | #include "gk20a/dbg_gpu_gk20a.h" |
24 | #include "gk20a/regops_gk20a.h" | ||
24 | #include "vgpu.h" | 25 | #include "vgpu.h" |
25 | #include "dbg_vgpu.h" | 26 | #include "dbg_vgpu.h" |
26 | 27 | ||
27 | #include <nvgpu/bug.h> | 28 | #include <nvgpu/bug.h> |
28 | 29 | ||
29 | int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, | 30 | int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, |
30 | struct nvgpu_dbg_gpu_reg_op *ops, | 31 | struct nvgpu_dbg_reg_op *ops, |
31 | u64 num_ops) | 32 | u64 num_ops) |
32 | { | 33 | { |
33 | struct channel_gk20a *ch; | 34 | struct channel_gk20a *ch; |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h index 8552a82e..178767a2 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h | |||
@@ -18,12 +18,12 @@ | |||
18 | #define _DBG_VGPU_H_ | 18 | #define _DBG_VGPU_H_ |
19 | 19 | ||
20 | struct dbg_session_gk20a; | 20 | struct dbg_session_gk20a; |
21 | struct nvgpu_dbg_gpu_reg_op; | 21 | struct nvgpu_dbg_reg_op; |
22 | struct dbg_profiler_object_data; | 22 | struct dbg_profiler_object_data; |
23 | struct gk20a; | 23 | struct gk20a; |
24 | 24 | ||
25 | int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, | 25 | int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, |
26 | struct nvgpu_dbg_gpu_reg_op *ops, | 26 | struct nvgpu_dbg_reg_op *ops, |
27 | u64 num_ops); | 27 | u64 num_ops); |
28 | int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate); | 28 | int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate); |
29 | bool vgpu_check_and_set_global_reservation( | 29 | bool vgpu_check_and_set_global_reservation( |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c index 7768b21d..f261d2ca 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c | |||
@@ -36,6 +36,7 @@ | |||
36 | #include "clk_vgpu.h" | 36 | #include "clk_vgpu.h" |
37 | #include "gk20a/tsg_gk20a.h" | 37 | #include "gk20a/tsg_gk20a.h" |
38 | #include "gk20a/channel_gk20a.h" | 38 | #include "gk20a/channel_gk20a.h" |
39 | #include "gk20a/regops_gk20a.h" | ||
39 | #include "gm20b/hal_gm20b.h" | 40 | #include "gm20b/hal_gm20b.h" |
40 | 41 | ||
41 | #include "common/linux/module.h" | 42 | #include "common/linux/module.h" |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 11a99bff..33d40cd5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -949,7 +949,7 @@ struct gpu_ops { | |||
949 | } debug; | 949 | } debug; |
950 | struct { | 950 | struct { |
951 | int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, | 951 | int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, |
952 | struct nvgpu_dbg_gpu_reg_op *ops, | 952 | struct nvgpu_dbg_reg_op *ops, |
953 | u64 num_ops); | 953 | u64 num_ops); |
954 | int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, | 954 | int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, |
955 | bool disable_powergate); | 955 | bool disable_powergate); |
@@ -1206,7 +1206,7 @@ struct gk20a { | |||
1206 | int dbg_timeout_disabled_refcount; /*refcount for timeout disable */ | 1206 | int dbg_timeout_disabled_refcount; /*refcount for timeout disable */ |
1207 | 1207 | ||
1208 | /* must have dbg_sessions_lock before use */ | 1208 | /* must have dbg_sessions_lock before use */ |
1209 | struct nvgpu_dbg_gpu_reg_op *dbg_regops_tmp_buf; | 1209 | struct nvgpu_dbg_reg_op *dbg_regops_tmp_buf; |
1210 | u32 dbg_regops_tmp_buf_ops; | 1210 | u32 dbg_regops_tmp_buf_ops; |
1211 | 1211 | ||
1212 | /* For perfbuf mapping */ | 1212 | /* For perfbuf mapping */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 03e1d567..82695e44 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -7749,7 +7749,7 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) | |||
7749 | } | 7749 | } |
7750 | 7750 | ||
7751 | int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | 7751 | int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, |
7752 | struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, | 7752 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, |
7753 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, | 7753 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, |
7754 | bool ch_is_curr_ctx) | 7754 | bool ch_is_curr_ctx) |
7755 | { | 7755 | { |
@@ -7990,7 +7990,7 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
7990 | } | 7990 | } |
7991 | 7991 | ||
7992 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | 7992 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, |
7993 | struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, | 7993 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, |
7994 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops) | 7994 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops) |
7995 | { | 7995 | { |
7996 | struct gk20a *g = ch->g; | 7996 | struct gk20a *g = ch->g; |
@@ -8279,7 +8279,7 @@ void gk20a_gr_resume_all_sms(struct gk20a *g) | |||
8279 | int gr_gk20a_set_sm_debug_mode(struct gk20a *g, | 8279 | int gr_gk20a_set_sm_debug_mode(struct gk20a *g, |
8280 | struct channel_gk20a *ch, u64 sms, bool enable) | 8280 | struct channel_gk20a *ch, u64 sms, bool enable) |
8281 | { | 8281 | { |
8282 | struct nvgpu_dbg_gpu_reg_op *ops; | 8282 | struct nvgpu_dbg_reg_op *ops; |
8283 | unsigned int i = 0, sm_id; | 8283 | unsigned int i = 0, sm_id; |
8284 | int err; | 8284 | int err; |
8285 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 8285 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
@@ -8453,7 +8453,7 @@ int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch) | |||
8453 | { | 8453 | { |
8454 | int err = 0; | 8454 | int err = 0; |
8455 | u32 cache_ctrl, regval; | 8455 | u32 cache_ctrl, regval; |
8456 | struct nvgpu_dbg_gpu_reg_op ops; | 8456 | struct nvgpu_dbg_reg_op ops; |
8457 | 8457 | ||
8458 | ops.op = REGOP(READ_32); | 8458 | ops.op = REGOP(READ_32); |
8459 | ops.type = REGOP(TYPE_GR_CTX); | 8459 | ops.type = REGOP(TYPE_GR_CTX); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 0df88988..5a5809fc 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -604,12 +604,12 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); | |||
604 | 604 | ||
605 | int gk20a_gr_suspend(struct gk20a *g); | 605 | int gk20a_gr_suspend(struct gk20a *g); |
606 | 606 | ||
607 | struct nvgpu_dbg_gpu_reg_op; | 607 | struct nvgpu_dbg_reg_op; |
608 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | 608 | int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, |
609 | struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, | 609 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, |
610 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops); | 610 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops); |
611 | int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | 611 | int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, |
612 | struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, | 612 | struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, |
613 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, | 613 | u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, |
614 | bool ch_is_curr_ctx); | 614 | bool ch_is_curr_ctx); |
615 | int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g, | 615 | int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index f0cf5205..06cd5051 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |||
@@ -22,9 +22,6 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <linux/err.h> | ||
26 | #include <uapi/linux/nvgpu.h> | ||
27 | |||
28 | #include "gk20a.h" | 25 | #include "gk20a.h" |
29 | #include "gr_gk20a.h" | 26 | #include "gr_gk20a.h" |
30 | #include "dbg_gpu_gk20a.h" | 27 | #include "dbg_gpu_gk20a.h" |
@@ -377,12 +374,12 @@ static const u32 gk20a_qctl_whitelist_ranges_count = | |||
377 | 374 | ||
378 | static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, | 375 | static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, |
379 | u32 *ctx_rd_count, u32 *ctx_wr_count, | 376 | u32 *ctx_rd_count, u32 *ctx_wr_count, |
380 | struct nvgpu_dbg_gpu_reg_op *ops, | 377 | struct nvgpu_dbg_reg_op *ops, |
381 | u32 op_count); | 378 | u32 op_count); |
382 | 379 | ||
383 | 380 | ||
384 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | 381 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, |
385 | struct nvgpu_dbg_gpu_reg_op *ops, | 382 | struct nvgpu_dbg_reg_op *ops, |
386 | u64 num_ops) | 383 | u64 num_ops) |
387 | { | 384 | { |
388 | int err = 0; | 385 | int err = 0; |
@@ -519,7 +516,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | |||
519 | 516 | ||
520 | 517 | ||
521 | static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s, | 518 | static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s, |
522 | struct nvgpu_dbg_gpu_reg_op *op) | 519 | struct nvgpu_dbg_reg_op *op) |
523 | { | 520 | { |
524 | int err = 0; | 521 | int err = 0; |
525 | 522 | ||
@@ -559,7 +556,7 @@ static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s, | |||
559 | } | 556 | } |
560 | 557 | ||
561 | static bool check_whitelists(struct dbg_session_gk20a *dbg_s, | 558 | static bool check_whitelists(struct dbg_session_gk20a *dbg_s, |
562 | struct nvgpu_dbg_gpu_reg_op *op, u32 offset) | 559 | struct nvgpu_dbg_reg_op *op, u32 offset) |
563 | { | 560 | { |
564 | struct gk20a *g = dbg_s->g; | 561 | struct gk20a *g = dbg_s->g; |
565 | bool valid = false; | 562 | bool valid = false; |
@@ -630,7 +627,7 @@ static bool check_whitelists(struct dbg_session_gk20a *dbg_s, | |||
630 | 627 | ||
631 | /* note: the op here has already been through validate_reg_op_info */ | 628 | /* note: the op here has already been through validate_reg_op_info */ |
632 | static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s, | 629 | static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s, |
633 | struct nvgpu_dbg_gpu_reg_op *op) | 630 | struct nvgpu_dbg_reg_op *op) |
634 | { | 631 | { |
635 | int err; | 632 | int err; |
636 | u32 buf_offset_lo, buf_offset_addr, num_offsets, offset; | 633 | u32 buf_offset_lo, buf_offset_addr, num_offsets, offset; |
@@ -689,7 +686,7 @@ static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s, | |||
689 | 686 | ||
690 | static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, | 687 | static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, |
691 | u32 *ctx_rd_count, u32 *ctx_wr_count, | 688 | u32 *ctx_rd_count, u32 *ctx_wr_count, |
692 | struct nvgpu_dbg_gpu_reg_op *ops, | 689 | struct nvgpu_dbg_reg_op *ops, |
693 | u32 op_count) | 690 | u32 op_count) |
694 | { | 691 | { |
695 | u32 i; | 692 | u32 i; |
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h index 4db79397..236fb52c 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h | |||
@@ -24,17 +24,63 @@ | |||
24 | #ifndef REGOPS_GK20A_H | 24 | #ifndef REGOPS_GK20A_H |
25 | #define REGOPS_GK20A_H | 25 | #define REGOPS_GK20A_H |
26 | 26 | ||
27 | /* | ||
28 | * Register operations | ||
29 | * All operations are targeted towards first channel | ||
30 | * attached to debug session | ||
31 | */ | ||
32 | /* valid op values */ | ||
33 | #define NVGPU_DBG_REG_OP_READ_32 (0x00000000) | ||
34 | #define NVGPU_DBG_REG_OP_WRITE_32 (0x00000001) | ||
35 | #define NVGPU_DBG_REG_OP_READ_64 (0x00000002) | ||
36 | #define NVGPU_DBG_REG_OP_WRITE_64 (0x00000003) | ||
37 | /* note: 8b ops are unsupported */ | ||
38 | #define NVGPU_DBG_REG_OP_READ_08 (0x00000004) | ||
39 | #define NVGPU_DBG_REG_OP_WRITE_08 (0x00000005) | ||
40 | |||
41 | /* valid type values */ | ||
42 | #define NVGPU_DBG_REG_OP_TYPE_GLOBAL (0x00000000) | ||
43 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX (0x00000001) | ||
44 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_TPC (0x00000002) | ||
45 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_SM (0x00000004) | ||
46 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_CROP (0x00000008) | ||
47 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_ZROP (0x00000010) | ||
48 | /*#define NVGPU_DBG_REG_OP_TYPE_FB (0x00000020)*/ | ||
49 | #define NVGPU_DBG_REG_OP_TYPE_GR_CTX_QUAD (0x00000040) | ||
50 | |||
51 | /* valid status values */ | ||
52 | #define NVGPU_DBG_REG_OP_STATUS_SUCCESS (0x00000000) | ||
53 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_OP (0x00000001) | ||
54 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_TYPE (0x00000002) | ||
55 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_OFFSET (0x00000004) | ||
56 | #define NVGPU_DBG_REG_OP_STATUS_UNSUPPORTED_OP (0x00000008) | ||
57 | #define NVGPU_DBG_REG_OP_STATUS_INVALID_MASK (0x00000010) | ||
58 | |||
59 | struct nvgpu_dbg_reg_op { | ||
60 | __u8 op; | ||
61 | __u8 type; | ||
62 | __u8 status; | ||
63 | __u8 quad; | ||
64 | __u32 group_mask; | ||
65 | __u32 sub_group_mask; | ||
66 | __u32 offset; | ||
67 | __u32 value_lo; | ||
68 | __u32 value_hi; | ||
69 | __u32 and_n_mask_lo; | ||
70 | __u32 and_n_mask_hi; | ||
71 | }; | ||
72 | |||
27 | struct regop_offset_range { | 73 | struct regop_offset_range { |
28 | u32 base:24; | 74 | u32 base:24; |
29 | u32 count:8; | 75 | u32 count:8; |
30 | }; | 76 | }; |
31 | 77 | ||
32 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, | 78 | int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, |
33 | struct nvgpu_dbg_gpu_reg_op *ops, | 79 | struct nvgpu_dbg_reg_op *ops, |
34 | u64 num_ops); | 80 | u64 num_ops); |
35 | 81 | ||
36 | /* turn seriously unwieldy names -> something shorter */ | 82 | /* turn seriously unwieldy names -> something shorter */ |
37 | #define REGOP(x) NVGPU_DBG_GPU_REG_OP_##x | 83 | #define REGOP(x) NVGPU_DBG_REG_OP_##x |
38 | 84 | ||
39 | bool reg_op_is_gr_ctx(u8 type); | 85 | bool reg_op_is_gr_ctx(u8 type); |
40 | bool reg_op_is_read(u8 op); | 86 | bool reg_op_is_read(u8 op); |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f0b77ebd..da28134e 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -2327,7 +2327,7 @@ void gr_gp10b_init_czf_bypass(struct gk20a *g) | |||
2327 | 2327 | ||
2328 | int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch) | 2328 | int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch) |
2329 | { | 2329 | { |
2330 | struct nvgpu_dbg_gpu_reg_op ops; | 2330 | struct nvgpu_dbg_reg_op ops; |
2331 | 2331 | ||
2332 | ops.op = REGOP(WRITE_32); | 2332 | ops.op = REGOP(WRITE_32); |
2333 | ops.type = REGOP(TYPE_GR_CTX); | 2333 | ops.type = REGOP(TYPE_GR_CTX); |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9e43941d..27fb7cb9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2584,7 +2584,7 @@ fail: | |||
2584 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | 2584 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, |
2585 | struct channel_gk20a *ch, u64 sms, bool enable) | 2585 | struct channel_gk20a *ch, u64 sms, bool enable) |
2586 | { | 2586 | { |
2587 | struct nvgpu_dbg_gpu_reg_op *ops; | 2587 | struct nvgpu_dbg_reg_op *ops; |
2588 | unsigned int i = 0, sm_id; | 2588 | unsigned int i = 0, sm_id; |
2589 | int err; | 2589 | int err; |
2590 | 2590 | ||