summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSeema Khowala <seemaj@nvidia.com>2017-02-28 14:03:09 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-09 15:23:29 -0500
commit4deb494ad114088f5253d02d9ec31f9aaeb2778a (patch)
tree7f13dee2f64dd4ebe121aaf820d16ec0aae529ff
parent2caea7576a42c5f6593c58229d51f74517e0c60c (diff)
gpu: nvgpu: debug dump enablement for t19x
Fifo ops added for dumping channel & ramfc status and pbdma & engine status. Change-Id: Icc739f4f05f0864721954489517fefdfa2fa608a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1302369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat
-rw-r--r--drivers/gpu/nvgpu/gk20a/debug_gk20a.c182
-rw-r--r--drivers/gpu/nvgpu/gk20a/debug_gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c188
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.h18
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h7
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c3
6 files changed, 229 insertions, 173 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
index 7c7d7ae6..89bfd0cf 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
@@ -33,49 +33,6 @@
33 33
34unsigned int gk20a_debug_trace_cmdbuf; 34unsigned int gk20a_debug_trace_cmdbuf;
35 35
36struct ch_state {
37 int pid;
38 int refs;
39 u32 inst_block[0];
40};
41
42static const char * const ccsr_chan_status_str[] = {
43 "idle",
44 "pending",
45 "pending_ctx_reload",
46 "pending_acquire",
47 "pending_acq_ctx_reload",
48 "on_pbdma",
49 "on_pbdma_and_eng",
50 "on_eng",
51 "on_eng_pending_acquire",
52 "on_eng_pending",
53 "on_pbdma_ctx_reload",
54 "on_pbdma_and_eng_ctx_reload",
55 "on_eng_ctx_reload",
56 "on_eng_pending_ctx_reload",
57 "on_eng_pending_acq_ctx_reload",
58};
59
60static const char * const chan_status_str[] = {
61 "invalid",
62 "valid",
63 "chsw_load",
64 "chsw_save",
65 "chsw_switch",
66};
67
68static const char * const ctx_status_str[] = {
69 "invalid",
70 "valid",
71 NULL,
72 NULL,
73 NULL,
74 "ctxsw_load",
75 "ctxsw_save",
76 "ctxsw_switch",
77};
78
79static inline void gk20a_debug_write_printk(void *ctx, const char *str, 36static inline void gk20a_debug_write_printk(void *ctx, const char *str,
80 size_t len) 37 size_t len)
81{ 38{
@@ -100,137 +57,13 @@ void gk20a_debug_output(struct gk20a_debug_output *o,
100 o->fn(o->ctx, o->buf, len); 57 o->fn(o->ctx, o->buf, len);
101} 58}
102 59
103static void gk20a_debug_show_channel(struct gk20a *g, 60static void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
104 struct gk20a_debug_output *o, 61 struct gk20a_debug_output *o)
105 u32 hw_chid,
106 struct ch_state *ch_state)
107{
108 u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid));
109 u32 status = ccsr_channel_status_v(channel);
110 u32 syncpointa, syncpointb;
111 u32 *inst_mem;
112 struct channel_gk20a *c = g->fifo.channel + hw_chid;
113 struct nvgpu_semaphore_int *hw_sema = NULL;
114
115 if (c->hw_sema)
116 hw_sema = c->hw_sema;
117
118 if (!ch_state)
119 return;
120
121 inst_mem = &ch_state->inst_block[0];
122
123 syncpointa = inst_mem[ram_fc_syncpointa_w()];
124 syncpointb = inst_mem[ram_fc_syncpointb_w()];
125
126 gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid,
127 dev_name(g->dev),
128 ch_state->pid,
129 ch_state->refs);
130 gk20a_debug_output(o, "%s in use %s %s\n",
131 ccsr_channel_enable_v(channel) ? "" : "not",
132 ccsr_chan_status_str[status],
133 ccsr_channel_busy_v(channel) ? "busy" : "not busy");
134 gk20a_debug_output(o, "TOP: %016llx PUT: %016llx GET: %016llx "
135 "FETCH: %016llx\nHEADER: %08x COUNT: %08x\n"
136 "SYNCPOINT %08x %08x SEMAPHORE %08x %08x %08x %08x\n",
137 (u64)inst_mem[ram_fc_pb_top_level_get_w()] +
138 ((u64)inst_mem[ram_fc_pb_top_level_get_hi_w()] << 32ULL),
139 (u64)inst_mem[ram_fc_pb_put_w()] +
140 ((u64)inst_mem[ram_fc_pb_put_hi_w()] << 32ULL),
141 (u64)inst_mem[ram_fc_pb_get_w()] +
142 ((u64)inst_mem[ram_fc_pb_get_hi_w()] << 32ULL),
143 (u64)inst_mem[ram_fc_pb_fetch_w()] +
144 ((u64)inst_mem[ram_fc_pb_fetch_hi_w()] << 32ULL),
145 inst_mem[ram_fc_pb_header_w()],
146 inst_mem[ram_fc_pb_count_w()],
147 syncpointa,
148 syncpointb,
149 inst_mem[ram_fc_semaphorea_w()],
150 inst_mem[ram_fc_semaphoreb_w()],
151 inst_mem[ram_fc_semaphorec_w()],
152 inst_mem[ram_fc_semaphored_w()]);
153 if (hw_sema)
154 gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
155 "next_val: 0x%08x addr: 0x%010llx\n",
156 readl(hw_sema->value),
157 atomic_read(&hw_sema->next_value),
158 nvgpu_hw_sema_addr(hw_sema));
159
160#ifdef CONFIG_TEGRA_GK20A
161 if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v())
162 && (pbdma_syncpointb_wait_switch_v(syncpointb) ==
163 pbdma_syncpointb_wait_switch_en_v()))
164 gk20a_debug_output(o, "%s on syncpt %u (%s) val %u\n",
165 (status == 3 || status == 8) ? "Waiting" : "Waited",
166 pbdma_syncpointb_syncpt_index_v(syncpointb),
167 nvhost_syncpt_get_name(g->host1x_dev,
168 pbdma_syncpointb_syncpt_index_v(syncpointb)),
169 pbdma_syncpointa_payload_v(syncpointa));
170#endif
171
172 gk20a_debug_output(o, "\n");
173}
174
175void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
176{ 62{
177 struct fifo_gk20a *f = &g->fifo; 63 struct fifo_gk20a *f = &g->fifo;
178 u32 chid; 64 u32 chid;
179 unsigned int i;
180 u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
181 u32 host_num_engines = nvgpu_get_litter_value(g,
182 GPU_LIT_HOST_NUM_ENGINES);
183
184 struct ch_state **ch_state; 65 struct ch_state **ch_state;
185 66
186 for (i = 0; i < host_num_pbdma; i++) {
187 u32 status = gk20a_readl(g, fifo_pbdma_status_r(i));
188 u32 chan_status = fifo_pbdma_status_chan_status_v(status);
189
190 gk20a_debug_output(o, "%s pbdma %d: ", dev_name(g->dev), i);
191 gk20a_debug_output(o,
192 "id: %d (%s), next_id: %d (%s) status: %s\n",
193 fifo_pbdma_status_id_v(status),
194 fifo_pbdma_status_id_type_v(status) ?
195 "tsg" : "channel",
196 fifo_pbdma_status_next_id_v(status),
197 fifo_pbdma_status_next_id_type_v(status) ?
198 "tsg" : "channel",
199 chan_status_str[chan_status]);
200 gk20a_debug_output(o, "PUT: %016llx GET: %016llx "
201 "FETCH: %08x HEADER: %08x\n",
202 (u64)gk20a_readl(g, pbdma_put_r(i)) +
203 ((u64)gk20a_readl(g, pbdma_put_hi_r(i)) << 32ULL),
204 (u64)gk20a_readl(g, pbdma_get_r(i)) +
205 ((u64)gk20a_readl(g, pbdma_get_hi_r(i)) << 32ULL),
206 gk20a_readl(g, pbdma_gp_fetch_r(i)),
207 gk20a_readl(g, pbdma_pb_header_r(i)));
208 }
209 gk20a_debug_output(o, "\n");
210
211 for (i = 0; i < host_num_engines; i++) {
212 u32 status = gk20a_readl(g, fifo_engine_status_r(i));
213 u32 ctx_status = fifo_engine_status_ctx_status_v(status);
214
215 gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i);
216 gk20a_debug_output(o,
217 "id: %d (%s), next_id: %d (%s), ctx: %s ",
218 fifo_engine_status_id_v(status),
219 fifo_engine_status_id_type_v(status) ?
220 "tsg" : "channel",
221 fifo_engine_status_next_id_v(status),
222 fifo_engine_status_next_id_type_v(status) ?
223 "tsg" : "channel",
224 ctx_status_str[ctx_status]);
225
226 if (fifo_engine_status_faulted_v(status))
227 gk20a_debug_output(o, "faulted ");
228 if (fifo_engine_status_engine_v(status))
229 gk20a_debug_output(o, "busy ");
230 gk20a_debug_output(o, "\n");
231 }
232 gk20a_debug_output(o, "\n");
233
234 ch_state = kzalloc(sizeof(*ch_state) 67 ch_state = kzalloc(sizeof(*ch_state)
235 * f->num_channels, GFP_KERNEL); 68 * f->num_channels, GFP_KERNEL);
236 if (!ch_state) { 69 if (!ch_state) {
@@ -265,13 +98,22 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
265 } 98 }
266 for (chid = 0; chid < f->num_channels; chid++) { 99 for (chid = 0; chid < f->num_channels; chid++) {
267 if (ch_state[chid]) { 100 if (ch_state[chid]) {
268 gk20a_debug_show_channel(g, o, chid, ch_state[chid]); 101 g->ops.fifo.dump_channel_status_ramfc(g, o, chid,
102 ch_state[chid]);
269 kfree(ch_state[chid]); 103 kfree(ch_state[chid]);
270 } 104 }
271 } 105 }
272 kfree(ch_state); 106 kfree(ch_state);
273} 107}
274 108
109void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
110{
111 g->ops.fifo.dump_pbdma_status(g, o);
112 g->ops.fifo.dump_eng_status(g, o);
113
114 gk20a_debug_dump_all_channel_status_ramfc(g, o);
115}
116
275static int gk20a_gr_dump_regs(struct device *dev, 117static int gk20a_gr_dump_regs(struct device *dev,
276 struct gk20a_debug_output *o) 118 struct gk20a_debug_output *o)
277{ 119{
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
index ac8e3236..213922b3 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Debug functionality 2 * GK20A Debug functionality
3 * 3 *
4 * Copyright (C) 2011-2016 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (C) 2011-2017 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -38,6 +38,4 @@ int gk20a_gr_debug_dump(struct device *pdev);
38void gk20a_debug_init(struct device *dev, const char *debugfs_symlink); 38void gk20a_debug_init(struct device *dev, const char *debugfs_symlink);
39void gk20a_init_debug_ops(struct gpu_ops *gops); 39void gk20a_init_debug_ops(struct gpu_ops *gops);
40void gk20a_debug_dump_device(void *dev); 40void gk20a_debug_dump_device(void *dev);
41
42
43#endif 41#endif
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 35d56ce4..b2efc1fa 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3554,6 +3554,191 @@ void gk20a_fifo_debugfs_init(struct device *dev)
3554} 3554}
3555#endif /* CONFIG_DEBUG_FS */ 3555#endif /* CONFIG_DEBUG_FS */
3556 3556
3557static const char * const ccsr_chan_status_str[] = {
3558 "idle",
3559 "pending",
3560 "pending_ctx_reload",
3561 "pending_acquire",
3562 "pending_acq_ctx_reload",
3563 "on_pbdma",
3564 "on_pbdma_and_eng",
3565 "on_eng",
3566 "on_eng_pending_acquire",
3567 "on_eng_pending",
3568 "on_pbdma_ctx_reload",
3569 "on_pbdma_and_eng_ctx_reload",
3570 "on_eng_ctx_reload",
3571 "on_eng_pending_ctx_reload",
3572 "on_eng_pending_acq_ctx_reload",
3573};
3574
3575const char * const pbdma_chan_eng_ctx_status_str[] = {
3576 "invalid",
3577 "valid",
3578 "NA",
3579 "NA",
3580 "NA",
3581 "load",
3582 "save",
3583 "switch",
3584};
3585
3586static const char * const not_found_str[] = {
3587 "NOT FOUND"
3588};
3589
3590const char *gk20a_decode_ccsr_chan_status(u32 index)
3591{
3592 if (index >= ARRAY_SIZE(ccsr_chan_status_str))
3593 return not_found_str[0];
3594 else
3595 return ccsr_chan_status_str[index];
3596}
3597
3598const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index)
3599{
3600 if (index >= ARRAY_SIZE(pbdma_chan_eng_ctx_status_str))
3601 return not_found_str[0];
3602 else
3603 return pbdma_chan_eng_ctx_status_str[index];
3604}
3605
3606void gk20a_dump_channel_status_ramfc(struct gk20a *g,
3607 struct gk20a_debug_output *o,
3608 u32 hw_chid,
3609 struct ch_state *ch_state)
3610{
3611 u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid));
3612 u32 status = ccsr_channel_status_v(channel);
3613 u32 syncpointa, syncpointb;
3614 u32 *inst_mem;
3615 struct channel_gk20a *c = g->fifo.channel + hw_chid;
3616 struct nvgpu_semaphore_int *hw_sema = NULL;
3617
3618 if (c->hw_sema)
3619 hw_sema = c->hw_sema;
3620
3621 if (!ch_state)
3622 return;
3623
3624 inst_mem = &ch_state->inst_block[0];
3625
3626 syncpointa = inst_mem[ram_fc_syncpointa_w()];
3627 syncpointb = inst_mem[ram_fc_syncpointb_w()];
3628
3629 gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid,
3630 dev_name(g->dev),
3631 ch_state->pid,
3632 ch_state->refs);
3633 gk20a_debug_output(o, "channel status: %s in use %s %s\n",
3634 ccsr_channel_enable_v(channel) ? "" : "not",
3635 gk20a_decode_ccsr_chan_status(status),
3636 ccsr_channel_busy_v(channel) ? "busy" : "not busy");
3637 gk20a_debug_output(o, "RAMFC : TOP: %016llx PUT: %016llx GET: %016llx "
3638 "FETCH: %016llx\nHEADER: %08x COUNT: %08x\n"
3639 "SYNCPOINT %08x %08x SEMAPHORE %08x %08x %08x %08x\n",
3640 (u64)inst_mem[ram_fc_pb_top_level_get_w()] +
3641 ((u64)inst_mem[ram_fc_pb_top_level_get_hi_w()] << 32ULL),
3642 (u64)inst_mem[ram_fc_pb_put_w()] +
3643 ((u64)inst_mem[ram_fc_pb_put_hi_w()] << 32ULL),
3644 (u64)inst_mem[ram_fc_pb_get_w()] +
3645 ((u64)inst_mem[ram_fc_pb_get_hi_w()] << 32ULL),
3646 (u64)inst_mem[ram_fc_pb_fetch_w()] +
3647 ((u64)inst_mem[ram_fc_pb_fetch_hi_w()] << 32ULL),
3648 inst_mem[ram_fc_pb_header_w()],
3649 inst_mem[ram_fc_pb_count_w()],
3650 syncpointa,
3651 syncpointb,
3652 inst_mem[ram_fc_semaphorea_w()],
3653 inst_mem[ram_fc_semaphoreb_w()],
3654 inst_mem[ram_fc_semaphorec_w()],
3655 inst_mem[ram_fc_semaphored_w()]);
3656 if (hw_sema)
3657 gk20a_debug_output(o, "SEMA STATE: value: 0x%08x "
3658 "next_val: 0x%08x addr: 0x%010llx\n",
3659 readl(hw_sema->value),
3660 atomic_read(&hw_sema->next_value),
3661 nvgpu_hw_sema_addr(hw_sema));
3662
3663#ifdef CONFIG_TEGRA_GK20A
3664 if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v())
3665 && (pbdma_syncpointb_wait_switch_v(syncpointb) ==
3666 pbdma_syncpointb_wait_switch_en_v()))
3667 gk20a_debug_output(o, "%s on syncpt %u (%s) val %u\n",
3668 (status == 3 || status == 8) ? "Waiting" : "Waited",
3669 pbdma_syncpointb_syncpt_index_v(syncpointb),
3670 nvhost_syncpt_get_name(g->host1x_dev,
3671 pbdma_syncpointb_syncpt_index_v(syncpointb)),
3672 pbdma_syncpointa_payload_v(syncpointa));
3673#endif
3674
3675 gk20a_debug_output(o, "\n");
3676}
3677
3678void gk20a_dump_pbdma_status(struct gk20a *g,
3679 struct gk20a_debug_output *o)
3680{
3681 u32 i, host_num_pbdma;
3682
3683 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
3684
3685 for (i = 0; i < host_num_pbdma; i++) {
3686 u32 status = gk20a_readl(g, fifo_pbdma_status_r(i));
3687 u32 chan_status = fifo_pbdma_status_chan_status_v(status);
3688
3689 gk20a_debug_output(o, "%s pbdma %d: ", dev_name(g->dev), i);
3690 gk20a_debug_output(o,
3691 "id: %d (%s), next_id: %d (%s) chan status: %s\n",
3692 fifo_pbdma_status_id_v(status),
3693 fifo_pbdma_status_id_type_v(status) ?
3694 "tsg" : "channel",
3695 fifo_pbdma_status_next_id_v(status),
3696 fifo_pbdma_status_next_id_type_v(status) ?
3697 "tsg" : "channel",
3698 gk20a_decode_pbdma_chan_eng_ctx_status(chan_status));
3699 gk20a_debug_output(o, "PUT: %016llx GET: %016llx "
3700 "FETCH: %08x HEADER: %08x\n",
3701 (u64)gk20a_readl(g, pbdma_put_r(i)) +
3702 ((u64)gk20a_readl(g, pbdma_put_hi_r(i)) << 32ULL),
3703 (u64)gk20a_readl(g, pbdma_get_r(i)) +
3704 ((u64)gk20a_readl(g, pbdma_get_hi_r(i)) << 32ULL),
3705 gk20a_readl(g, pbdma_gp_fetch_r(i)),
3706 gk20a_readl(g, pbdma_pb_header_r(i)));
3707 }
3708 gk20a_debug_output(o, "\n");
3709}
3710
3711void gk20a_dump_eng_status(struct gk20a *g,
3712 struct gk20a_debug_output *o)
3713{
3714 u32 i, host_num_engines;
3715
3716 host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
3717
3718 for (i = 0; i < host_num_engines; i++) {
3719 u32 status = gk20a_readl(g, fifo_engine_status_r(i));
3720 u32 ctx_status = fifo_engine_status_ctx_status_v(status);
3721
3722 gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i);
3723 gk20a_debug_output(o,
3724 "id: %d (%s), next_id: %d (%s), ctx status: %s ",
3725 fifo_engine_status_id_v(status),
3726 fifo_engine_status_id_type_v(status) ?
3727 "tsg" : "channel",
3728 fifo_engine_status_next_id_v(status),
3729 fifo_engine_status_next_id_type_v(status) ?
3730 "tsg" : "channel",
3731 gk20a_decode_pbdma_chan_eng_ctx_status(ctx_status));
3732
3733 if (fifo_engine_status_faulted_v(status))
3734 gk20a_debug_output(o, "faulted ");
3735 if (fifo_engine_status_engine_v(status))
3736 gk20a_debug_output(o, "busy ");
3737 gk20a_debug_output(o, "\n");
3738 }
3739 gk20a_debug_output(o, "\n");
3740}
3741
3557void gk20a_init_fifo(struct gpu_ops *gops) 3742void gk20a_init_fifo(struct gpu_ops *gops)
3558{ 3743{
3559 gk20a_init_channel(gops); 3744 gk20a_init_channel(gops);
@@ -3578,4 +3763,7 @@ void gk20a_init_fifo(struct gpu_ops *gops)
3578 gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry; 3763 gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry;
3579 gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry; 3764 gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry;
3580 gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc; 3765 gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc;
3766 gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
3767 gops->fifo.dump_eng_status = gk20a_dump_eng_status;
3768 gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc;
3581} 3769}
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 75c801c6..37808928 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -23,6 +23,7 @@
23 23
24#include "channel_gk20a.h" 24#include "channel_gk20a.h"
25#include "tsg_gk20a.h" 25#include "tsg_gk20a.h"
26#include "debug_gk20a.h"
26 27
27#define MAX_RUNLIST_BUFFERS 2 28#define MAX_RUNLIST_BUFFERS 2
28 29
@@ -202,6 +203,12 @@ static inline const char *gk20a_fifo_interleave_level_name(u32 interleave_level)
202 } 203 }
203} 204}
204 205
206struct ch_state {
207 int pid;
208 int refs;
209 u32 inst_block[0];
210};
211
205int gk20a_init_fifo_support(struct gk20a *g); 212int gk20a_init_fifo_support(struct gk20a *g);
206 213
207int gk20a_init_fifo_setup_hw(struct gk20a *g); 214int gk20a_init_fifo_setup_hw(struct gk20a *g);
@@ -313,4 +320,15 @@ void gk20a_fifo_profile_release(struct gk20a *g,
313 struct fifo_profile_gk20a *profile); 320 struct fifo_profile_gk20a *profile);
314#endif 321#endif
315 322
323void gk20a_dump_channel_status_ramfc(struct gk20a *g,
324 struct gk20a_debug_output *o,
325 u32 hw_chid,
326 struct ch_state *ch_state);
327void gk20a_dump_pbdma_status(struct gk20a *g,
328 struct gk20a_debug_output *o);
329void gk20a_dump_eng_status(struct gk20a *g,
330 struct gk20a_debug_output *o);
331const char *gk20a_decode_ccsr_chan_status(u32 index);
332const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index);
333
316#endif /*__GR_GK20A_H__*/ 334#endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index e55753fe..12c9a3ea 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -438,6 +438,13 @@ struct gpu_ops {
438 void (*free_channel_ctx_header)(struct channel_gk20a *ch); 438 void (*free_channel_ctx_header)(struct channel_gk20a *ch);
439 bool (*is_fault_engine_subid_gpc)(struct gk20a *g, 439 bool (*is_fault_engine_subid_gpc)(struct gk20a *g,
440 u32 engine_subid); 440 u32 engine_subid);
441 void (*dump_pbdma_status)(struct gk20a *g,
442 struct gk20a_debug_output *o);
443 void (*dump_eng_status)(struct gk20a *g,
444 struct gk20a_debug_output *o);
445 void (*dump_channel_status_ramfc)(struct gk20a *g,
446 struct gk20a_debug_output *o, u32 hw_chid,
447 struct ch_state *ch_state);
441 } fifo; 448 } fifo;
442 struct pmu_v { 449 struct pmu_v {
443 /*used for change of enum zbc update cmd id from ver 0 to ver1*/ 450 /*used for change of enum zbc update cmd id from ver 0 to ver1*/
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 696dd3a5..27ddc968 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -171,4 +171,7 @@ void gm20b_init_fifo(struct gpu_ops *gops)
171 gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry; 171 gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry;
172 gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry; 172 gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry;
173 gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc; 173 gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc;
174 gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
175 gops->fifo.dump_eng_status = gk20a_dump_eng_status;
176 gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc;
174} 177}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 15:22:19 -0400