diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2017-04-10 12:38:59 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-17 11:14:17 -0400 |
commit | 4ba206aacca15134d60c73d94a4d9568064bcc22 (patch) | |
tree | cd6fdabbea7edc0f6a08bc76eee114364f5b076d | |
parent | 59d2c753a0e8a2e93d23ca415eb00fc81e068e78 (diff) |
gpu: nvgpu: Use PMU ver to check ZBC support.
From Volta onwards, new DSS ZBC registers are
added for ZBC feature and save/restore of new
ZBC reglist is taken care by ctxsw firmware.
Therefore, PMU should save ZBC reglist only
for PRE-volta chips.
JIRA GPUT19X-20
Change-Id: I7d92274208ca42cc77bf57ea3cc416b5ecf32842
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1460244
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 15 |
2 files changed, 13 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 9760ba35..85878423 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -481,6 +481,7 @@ struct gpu_ops { | |||
481 | struct pmu_v { | 481 | struct pmu_v { |
482 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 482 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
483 | u32 cmd_id_zbc_table_update; | 483 | u32 cmd_id_zbc_table_update; |
484 | bool is_pmu_zbc_save_supported; | ||
484 | u32 (*get_pmu_cmdline_args_size)(struct pmu_gk20a *pmu); | 485 | u32 (*get_pmu_cmdline_args_size)(struct pmu_gk20a *pmu); |
485 | void (*set_pmu_cmdline_args_cpu_freq)(struct pmu_gk20a *pmu, | 486 | void (*set_pmu_cmdline_args_cpu_freq)(struct pmu_gk20a *pmu, |
486 | u32 freq); | 487 | u32 freq); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index cb9e1ba1..49b9e78d 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -1482,6 +1482,7 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
1482 | set_perfmon_cntr_group_id_v2; | 1482 | set_perfmon_cntr_group_id_v2; |
1483 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1483 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1484 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1484 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; |
1485 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | ||
1485 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1486 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1486 | pmu_cmdline_size_v4; | 1487 | pmu_cmdline_size_v4; |
1487 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1488 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1583,6 +1584,7 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
1583 | set_perfmon_cntr_group_id_v2; | 1584 | set_perfmon_cntr_group_id_v2; |
1584 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1585 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1585 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1586 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; |
1587 | g->ops.pmu_ver.is_pmu_zbc_save_supported = false; | ||
1586 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1588 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1587 | pmu_cmdline_size_v5; | 1589 | pmu_cmdline_size_v5; |
1588 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1590 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1690,6 +1692,7 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
1690 | set_perfmon_cntr_group_id_v2; | 1692 | set_perfmon_cntr_group_id_v2; |
1691 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1693 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1692 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1694 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; |
1695 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | ||
1693 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1696 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1694 | pmu_cmdline_size_v5; | 1697 | pmu_cmdline_size_v5; |
1695 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1698 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1810,6 +1813,7 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
1810 | set_perfmon_cntr_group_id_v2; | 1813 | set_perfmon_cntr_group_id_v2; |
1811 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1814 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1812 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1815 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; |
1816 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | ||
1813 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1817 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1814 | pmu_cmdline_size_v3; | 1818 | pmu_cmdline_size_v3; |
1815 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1819 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -1912,6 +1916,7 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
1912 | set_perfmon_cntr_group_id_v2; | 1916 | set_perfmon_cntr_group_id_v2; |
1913 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | 1917 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; |
1914 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 1918 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; |
1919 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | ||
1915 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | 1920 | g->ops.pmu_ver.get_pmu_cmdline_args_size = |
1916 | pmu_cmdline_size_v2; | 1921 | pmu_cmdline_size_v2; |
1917 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | 1922 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = |
@@ -2007,6 +2012,7 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
2007 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = | 2012 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = |
2008 | pg_cmd_eng_buf_load_set_dma_idx_v0; | 2013 | pg_cmd_eng_buf_load_set_dma_idx_v0; |
2009 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | 2014 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; |
2015 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | ||
2010 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; | 2016 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; |
2011 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; | 2017 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; |
2012 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; | 2018 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; |
@@ -2108,6 +2114,7 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
2108 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = | 2114 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = |
2109 | pg_cmd_eng_buf_load_set_dma_idx_v0; | 2115 | pg_cmd_eng_buf_load_set_dma_idx_v0; |
2110 | g->ops.pmu_ver.cmd_id_zbc_table_update = 14; | 2116 | g->ops.pmu_ver.cmd_id_zbc_table_update = 14; |
2117 | g->ops.pmu_ver.is_pmu_zbc_save_supported = true; | ||
2111 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; | 2118 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0; |
2112 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; | 2119 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0; |
2113 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; | 2120 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0; |
@@ -3435,9 +3442,11 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
3435 | pmu->initialized = true; | 3442 | pmu->initialized = true; |
3436 | pmu->pmu_state = PMU_STATE_STARTED; | 3443 | pmu->pmu_state = PMU_STATE_STARTED; |
3437 | 3444 | ||
3438 | pmu->zbc_ready = true; | 3445 | if (g->ops.pmu_ver.is_pmu_zbc_save_supported) { |
3439 | /* Save zbc table after PMU is initialized. */ | 3446 | /* Save zbc table after PMU is initialized. */ |
3440 | gk20a_pmu_save_zbc(g, 0xf); | 3447 | pmu->zbc_ready = true; |
3448 | gk20a_pmu_save_zbc(g, 0xf); | ||
3449 | } | ||
3441 | 3450 | ||
3442 | if (g->elpg_enabled) { | 3451 | if (g->elpg_enabled) { |
3443 | /* Init reg with prod values*/ | 3452 | /* Init reg with prod values*/ |