diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2016-04-21 19:35:44 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-21 14:33:23 -0400 |
commit | 47e3d2e90511b1cba68e46233896a918b32b5d33 (patch) | |
tree | 2840d2cc820690f27ad881a80774dd26cebc5302 | |
parent | 4df6cd4a345d9a564f2235bc6a20ebb4614c2b04 (diff) |
gpu: nvgpu: fix engine reset in FECS trace
In virtualization case, VM server is the only one
allowed to write to ctxsw ring buffer. It will
also generate an event in case of engine reset.
Only generate a tracepoint on Guest OS side.
EVLR-314
Change-Id: I2cb09780a9b41237fe196ef1f3515923f36a24a4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1130743
(cherry picked from commit 4bbf9538e2a3375eb86b2feea6c605c3eec2ca40)
Reviewed-on: http://git-master/r/1133614
(cherry picked from commit 2076d944db41b37143c27795b3cffd88e99e0b00)
Reviewed-on: http://git-master/r/1150046
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 2 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 2 |
5 files changed, 14 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index d99c48fb..69da03e1 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -885,11 +885,9 @@ static void gk20a_free_channel(struct channel_gk20a *ch) | |||
885 | mutex_lock(&g->fifo.gr_reset_mutex); | 885 | mutex_lock(&g->fifo.gr_reset_mutex); |
886 | /* if lock is already taken, a reset is taking place | 886 | /* if lock is already taken, a reset is taking place |
887 | so no need to repeat */ | 887 | so no need to repeat */ |
888 | if (!was_reset) { | 888 | if (!was_reset) |
889 | gk20a_ctxsw_trace_channel_reset(g, ch); | ||
890 | gk20a_fifo_reset_engine(g, | 889 | gk20a_fifo_reset_engine(g, |
891 | g->fifo.deferred_fault_engines); | 890 | g->fifo.deferred_fault_engines); |
892 | } | ||
893 | mutex_unlock(&g->fifo.gr_reset_mutex); | 891 | mutex_unlock(&g->fifo.gr_reset_mutex); |
894 | g->fifo.deferred_fault_engines = 0; | 892 | g->fifo.deferred_fault_engines = 0; |
895 | g->fifo.deferred_reset_pending = false; | 893 | g->fifo.deferred_reset_pending = false; |
diff --git a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c index 3f39ced1..0fa9e65a 100644 --- a/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctxsw_trace_gk20a.c | |||
@@ -626,16 +626,16 @@ void gk20a_ctxsw_trace_channel_reset(struct gk20a *g, struct channel_gk20a *ch) | |||
626 | #ifdef CONFIG_GK20A_CTXSW_TRACE | 626 | #ifdef CONFIG_GK20A_CTXSW_TRACE |
627 | struct nvgpu_ctxsw_trace_entry entry = { | 627 | struct nvgpu_ctxsw_trace_entry entry = { |
628 | .vmid = 0, | 628 | .vmid = 0, |
629 | .tag = NVGPU_CTXSW_TAG_RESET, | 629 | .tag = NVGPU_CTXSW_TAG_ENGINE_RESET, |
630 | .timestamp = gk20a_read_ptimer(g), | 630 | .timestamp = gk20a_read_ptimer(g), |
631 | .context_id = 0, | 631 | .context_id = 0, |
632 | .pid = ch->pid, | 632 | .pid = ch->pid, |
633 | }; | 633 | }; |
634 | 634 | ||
635 | gk20a_ctxsw_trace_write(g, &entry); | 635 | gk20a_ctxsw_trace_write(g, &entry); |
636 | gk20a_ctxsw_trace_wake_up(g, 0); | ||
636 | #endif | 637 | #endif |
637 | trace_gk20a_channel_reset(ch->hw_chid, ch->tsgid); | 638 | trace_gk20a_channel_reset(ch->hw_chid, ch->tsgid); |
638 | gk20a_ctxsw_trace_wake_up(g, 0); | ||
639 | } | 639 | } |
640 | 640 | ||
641 | void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) | 641 | void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) |
@@ -643,7 +643,7 @@ void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) | |||
643 | #ifdef CONFIG_GK20A_CTXSW_TRACE | 643 | #ifdef CONFIG_GK20A_CTXSW_TRACE |
644 | struct nvgpu_ctxsw_trace_entry entry = { | 644 | struct nvgpu_ctxsw_trace_entry entry = { |
645 | .vmid = 0, | 645 | .vmid = 0, |
646 | .tag = NVGPU_CTXSW_TAG_RESET, | 646 | .tag = NVGPU_CTXSW_TAG_ENGINE_RESET, |
647 | .timestamp = gk20a_read_ptimer(g), | 647 | .timestamp = gk20a_read_ptimer(g), |
648 | .context_id = 0, | 648 | .context_id = 0, |
649 | .pid = 0, | 649 | .pid = 0, |
@@ -657,9 +657,9 @@ void gk20a_ctxsw_trace_tsg_reset(struct gk20a *g, struct tsg_gk20a *tsg) | |||
657 | entry.pid = ch->pid; | 657 | entry.pid = ch->pid; |
658 | 658 | ||
659 | gk20a_ctxsw_trace_write(g, &entry); | 659 | gk20a_ctxsw_trace_write(g, &entry); |
660 | gk20a_ctxsw_trace_wake_up(g, 0); | ||
660 | #endif | 661 | #endif |
661 | trace_gk20a_channel_reset(~0, tsg->tsgid); | 662 | trace_gk20a_channel_reset(~0, tsg->tsgid); |
662 | gk20a_ctxsw_trace_wake_up(g, 0); | ||
663 | } | 663 | } |
664 | 664 | ||
665 | void gk20a_ctxsw_trace_init_ops(struct gpu_ops *ops) | 665 | void gk20a_ctxsw_trace_init_ops(struct gpu_ops *ops) |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index b0e2ce1f..cf97b33a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1082,15 +1082,16 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1082 | mutex_lock(&g->fifo.gr_reset_mutex); | 1082 | mutex_lock(&g->fifo.gr_reset_mutex); |
1083 | /* if lock is already taken, a reset is taking place | 1083 | /* if lock is already taken, a reset is taking place |
1084 | so no need to repeat */ | 1084 | so no need to repeat */ |
1085 | if (!was_reset) { | 1085 | if (!was_reset) |
1086 | if (ch) | ||
1087 | gk20a_ctxsw_trace_channel_reset(g, ch); | ||
1088 | else | ||
1089 | gk20a_ctxsw_trace_tsg_reset(g, tsg); | ||
1090 | gk20a_fifo_reset_engine(g, engine_id); | 1086 | gk20a_fifo_reset_engine(g, engine_id); |
1091 | } | ||
1092 | mutex_unlock(&g->fifo.gr_reset_mutex); | 1087 | mutex_unlock(&g->fifo.gr_reset_mutex); |
1093 | } | 1088 | } |
1089 | |||
1090 | if (ch) | ||
1091 | gk20a_ctxsw_trace_channel_reset(g, ch); | ||
1092 | else if (tsg) | ||
1093 | gk20a_ctxsw_trace_tsg_reset(g, tsg); | ||
1094 | |||
1094 | /* disable the channel/TSG from hw and increment | 1095 | /* disable the channel/TSG from hw and increment |
1095 | * syncpoints */ | 1096 | * syncpoints */ |
1096 | 1097 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 83fd65ff..8fcc7cc1 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -630,7 +630,7 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) | |||
630 | gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u", | 630 | gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u", |
631 | info->type, info->chid); | 631 | info->type, info->chid); |
632 | 632 | ||
633 | gk20a_ctxsw_trace_channel_reset(g, ch); | 633 | trace_gk20a_channel_reset(ch->hw_chid, ch->tsgid); |
634 | 634 | ||
635 | switch (info->type) { | 635 | switch (info->type) { |
636 | case TEGRA_VGPU_FIFO_INTR_PBDMA: | 636 | case TEGRA_VGPU_FIFO_INTR_PBDMA: |
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 76a6b1cc..3bc1ca3d 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -1367,7 +1367,7 @@ struct nvgpu_as_map_buffer_batch_args { | |||
1367 | #define NVGPU_CTXSW_TAG_SAVE_END 0x03 | 1367 | #define NVGPU_CTXSW_TAG_SAVE_END 0x03 |
1368 | #define NVGPU_CTXSW_TAG_RESTORE_START 0x04 | 1368 | #define NVGPU_CTXSW_TAG_RESTORE_START 0x04 |
1369 | #define NVGPU_CTXSW_TAG_CONTEXT_START 0x05 | 1369 | #define NVGPU_CTXSW_TAG_CONTEXT_START 0x05 |
1370 | #define NVGPU_CTXSW_TAG_RESET 0xfe | 1370 | #define NVGPU_CTXSW_TAG_ENGINE_RESET 0xfe |
1371 | #define NVGPU_CTXSW_TAG_INVALID_TIMESTAMP 0xff | 1371 | #define NVGPU_CTXSW_TAG_INVALID_TIMESTAMP 0xff |
1372 | #define NVGPU_CTXSW_TAG_LAST \ | 1372 | #define NVGPU_CTXSW_TAG_LAST \ |
1373 | NVGPU_CTXSW_TAG_INVALID_TIMESTAMP | 1373 | NVGPU_CTXSW_TAG_INVALID_TIMESTAMP |