diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-12 17:21:12 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-13 12:14:03 -0400 |
commit | 45355f00e7de9068f403682044f550026fa7e86e (patch) | |
tree | 276a96965318a4f4e8e1e3a9b2d5f0eb650ac30c | |
parent | 64050935e931df0650a82c9f28bc9a3a331f4152 (diff) |
gpu: nvgpu: use hww_esr_reset field to reset hwww_esr
Use hww_esr_reset field to clear hww errors
Change-Id: I4b5da20c8a4bcfe2dea357d3d2ebd53678673b48
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1500965
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0fd27598..f56702dc 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -6558,14 +6558,16 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6558 | if (exception & gr_exception_fe_m()) { | 6558 | if (exception & gr_exception_fe_m()) { |
6559 | u32 fe = gk20a_readl(g, gr_fe_hww_esr_r()); | 6559 | u32 fe = gk20a_readl(g, gr_fe_hww_esr_r()); |
6560 | nvgpu_err(g, "fe warning %08x", fe); | 6560 | nvgpu_err(g, "fe warning %08x", fe); |
6561 | gk20a_writel(g, gr_fe_hww_esr_r(), fe); | 6561 | gk20a_writel(g, gr_fe_hww_esr_r(), |
6562 | gr_fe_hww_esr_reset_active_f()); | ||
6562 | need_reset |= -EFAULT; | 6563 | need_reset |= -EFAULT; |
6563 | } | 6564 | } |
6564 | 6565 | ||
6565 | if (exception & gr_exception_memfmt_m()) { | 6566 | if (exception & gr_exception_memfmt_m()) { |
6566 | u32 memfmt = gk20a_readl(g, gr_memfmt_hww_esr_r()); | 6567 | u32 memfmt = gk20a_readl(g, gr_memfmt_hww_esr_r()); |
6567 | nvgpu_err(g, "memfmt exception %08x", memfmt); | 6568 | nvgpu_err(g, "memfmt exception %08x", memfmt); |
6568 | gk20a_writel(g, gr_memfmt_hww_esr_r(), memfmt); | 6569 | gk20a_writel(g, gr_memfmt_hww_esr_r(), |
6570 | gr_memfmt_hww_esr_reset_active_f()); | ||
6569 | need_reset |= -EFAULT; | 6571 | need_reset |= -EFAULT; |
6570 | } | 6572 | } |
6571 | 6573 | ||
@@ -6594,7 +6596,8 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6594 | if (exception & gr_exception_ds_m()) { | 6596 | if (exception & gr_exception_ds_m()) { |
6595 | u32 ds = gk20a_readl(g, gr_ds_hww_esr_r()); | 6597 | u32 ds = gk20a_readl(g, gr_ds_hww_esr_r()); |
6596 | nvgpu_err(g, "ds exception %08x", ds); | 6598 | nvgpu_err(g, "ds exception %08x", ds); |
6597 | gk20a_writel(g, gr_ds_hww_esr_r(), ds); | 6599 | gk20a_writel(g, gr_ds_hww_esr_r(), |
6600 | gr_ds_hww_esr_reset_task_f()); | ||
6598 | need_reset |= -EFAULT; | 6601 | need_reset |= -EFAULT; |
6599 | } | 6602 | } |
6600 | 6603 | ||