diff options
author | David Nieto <dmartineznie@nvidia.com> | 2017-12-17 15:39:08 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-12-28 13:01:39 -0500 |
commit | 443977daa12f74cc77c5c48fb2166c1f9c5b6795 (patch) | |
tree | 70f532866f198b7e1228c55351ad541b6b692c98 | |
parent | 8fb6a8562ec033d2d1319f91377cd1782f593979 (diff) |
gpu: nvgpu: Add support for GV100 SKU 250
Bug 2040925
Change-Id: Ied06b199fd87411847b9987496c56276f8ebf89c
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1623709
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/pci.c | 86 |
1 files changed, 84 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c index 296d0a7c..342fa5af 100644 --- a/drivers/gpu/nvgpu/common/linux/pci.c +++ b/drivers/gpu/nvgpu/common/linux/pci.c | |||
@@ -280,7 +280,77 @@ static struct gk20a_platform nvgpu_pci_device[] = { | |||
280 | .hardcode_sw_threshold = false, | 280 | .hardcode_sw_threshold = false, |
281 | .run_preos = true, | 281 | .run_preos = true, |
282 | .tsg_required = true, | 282 | .tsg_required = true, |
283 | } | 283 | }, |
284 | { | ||
285 | /* ptimer src frequency in hz */ | ||
286 | .ptimer_src_freq = 31250000, | ||
287 | |||
288 | .probe = nvgpu_pci_tegra_probe, | ||
289 | .remove = nvgpu_pci_tegra_remove, | ||
290 | |||
291 | /* power management configuration */ | ||
292 | .railgate_delay_init = 500, | ||
293 | .can_railgate_init = false, | ||
294 | .can_elpg_init = false, | ||
295 | .enable_elpg = false, | ||
296 | .enable_elcg = false, | ||
297 | .enable_slcg = false, | ||
298 | .enable_blcg = false, | ||
299 | .enable_mscg = false, | ||
300 | .can_slcg = false, | ||
301 | .can_blcg = false, | ||
302 | .can_elcg = false, | ||
303 | .default_pri_timeout = 0x3ff, | ||
304 | |||
305 | .disable_aspm = true, | ||
306 | |||
307 | /* power management callbacks */ | ||
308 | .is_railgated = nvgpu_pci_tegra_is_railgated, | ||
309 | .clk_round_rate = nvgpu_pci_clk_round_rate, | ||
310 | |||
311 | .ch_wdt_timeout_ms = 7000, | ||
312 | |||
313 | .honors_aperture = true, | ||
314 | .vbios_min_version = 0x88000126, | ||
315 | .hardcode_sw_threshold = false, | ||
316 | .run_preos = true, | ||
317 | .tsg_required = true, | ||
318 | }, | ||
319 | { /* SKU250 */ | ||
320 | /* ptimer src frequency in hz */ | ||
321 | .ptimer_src_freq = 31250000, | ||
322 | |||
323 | .probe = nvgpu_pci_tegra_probe, | ||
324 | .remove = nvgpu_pci_tegra_remove, | ||
325 | |||
326 | /* power management configuration */ | ||
327 | .railgate_delay_init = 500, | ||
328 | .can_railgate_init = false, | ||
329 | .can_elpg_init = false, | ||
330 | .enable_elpg = false, | ||
331 | .enable_elcg = false, | ||
332 | .enable_slcg = false, | ||
333 | .enable_blcg = false, | ||
334 | .enable_mscg = false, | ||
335 | .can_slcg = false, | ||
336 | .can_blcg = false, | ||
337 | .can_elcg = false, | ||
338 | .default_pri_timeout = 0x3ff, | ||
339 | |||
340 | .disable_aspm = true, | ||
341 | |||
342 | /* power management callbacks */ | ||
343 | .is_railgated = nvgpu_pci_tegra_is_railgated, | ||
344 | .clk_round_rate = nvgpu_pci_clk_round_rate, | ||
345 | |||
346 | .ch_wdt_timeout_ms = 7000, | ||
347 | |||
348 | .honors_aperture = true, | ||
349 | .vbios_min_version = 0x1, | ||
350 | .hardcode_sw_threshold = false, | ||
351 | .run_preos = true, | ||
352 | .tsg_required = true, | ||
353 | }, | ||
284 | }; | 354 | }; |
285 | 355 | ||
286 | static struct pci_device_id nvgpu_pci_table[] = { | 356 | static struct pci_device_id nvgpu_pci_table[] = { |
@@ -318,7 +388,19 @@ static struct pci_device_id nvgpu_pci_table[] = { | |||
318 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1db0), | 388 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1db0), |
319 | .class = PCI_BASE_CLASS_DISPLAY << 16, | 389 | .class = PCI_BASE_CLASS_DISPLAY << 16, |
320 | .class_mask = 0xff << 16, | 390 | .class_mask = 0xff << 16, |
321 | .driver_data = 4, | 391 | .driver_data = 5, |
392 | }, | ||
393 | { | ||
394 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1dbe), | ||
395 | .class = PCI_BASE_CLASS_DISPLAY << 16, | ||
396 | .class_mask = 0xff << 16, | ||
397 | .driver_data = 6, | ||
398 | }, | ||
399 | { | ||
400 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1df1), | ||
401 | .class = PCI_BASE_CLASS_DISPLAY << 16, | ||
402 | .class_mask = 0xff << 16, | ||
403 | .driver_data = 7, | ||
322 | }, | 404 | }, |
323 | {} | 405 | {} |
324 | }; | 406 | }; |